cucapra / fodlam

Related projects ⓘ

Alternatives and complementary repositories for fodlam

• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆59Updated 3 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆44Updated 2 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆31Updated 2 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆33Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆70Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated 7 months ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆44Updated 6 years ago
• awai54st / LUTNet
  ☆55Updated 4 years ago
• BradMcDanel / column-combine
  ☆27Updated 4 years ago
• hsharma35 / bitfusion
  Simulator for BitFusion
  ☆92Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆35Updated 4 years ago
• gopala-kr / DL-on-Silicon
  research, experimentation and implementation of hardware-agnostic accelerated DL framework
  ☆33Updated 3 weeks ago
• maestro-project / gamma
  ☆34Updated 4 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• UCLA-VAST / CLINK
  Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
  ☆17Updated 5 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆64Updated 5 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆91Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 7 years ago
• ARM-software / DeepFreeze
  ☆40Updated 4 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆29Updated 2 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆87Updated 3 years ago
• aravinds92 / Systolic-Array
  Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
  ☆12Updated 8 years ago
• maestro-project / magma
  ☆16Updated 2 years ago
• microideax / Open-Dnn
  ☆27Updated 5 years ago