CMU-SAFARI / MemBen
Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 paper: Ghose et al., "Demystifying Complex Workload-DRAM Interactions: An Experimental Study" at https://arxiv.org/pdf/1902.07609.pdf.
☆19Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for MemBen
- ☆18Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- A fast and scalable x86-64 multicore simulator☆31Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- Tutorial Material from the SST Team☆18Updated 6 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 4 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- Creating beautiful gem5 simulations☆45Updated 3 years ago
- ☆18Updated 4 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆17Updated 7 months ago
- Artifact, reproducibility, and testing utilites for gem5☆20Updated 3 years ago
- ☆13Updated 9 years ago
- A parallel and distributed simulator for thousand-core chips☆22Updated 6 years ago
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆13Updated 8 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 8 years ago
- Examples of DPU programs using the UPMEM DPU SDK☆36Updated 2 months ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆49Updated 5 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆15Updated 3 years ago
- DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is inte…☆76Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆15Updated 4 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆51Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆17Updated 7 months ago
- Memory System Microbenchmarks☆61Updated last year
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆31Updated this week
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago