Alternatives and similar repositories for CUDA-SPICE-Circuit-Sim:

Users that are interested in CUDA-SPICE-Circuit-Sim are comparing it to the libraries listed below

• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆32Updated this week
• ckchengucsd / ILP-SAT-Detailed-Router
  ILP SAT Detailed Router
  ☆11Updated 4 years ago
• aolofsson / POSH
  ☆40Updated 5 years ago
• aolofsson / IDEA
  ☆32Updated 5 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_pr
  Primitives for GF180MCU provided by GlobalFoundries.
  ☆48Updated last year
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆38Updated 2 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated 3 weeks ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆47Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆47Updated 9 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 2 months ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆73Updated last month
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 2 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 3 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆99Updated 9 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated last year
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆13Updated 8 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆27Updated 4 years ago
• pulp-platform / cheshire-ihp130-o
  ☆31Updated 3 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆73Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 9 months ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆37Updated this week
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 2 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆28Updated 5 months ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆59Updated this week
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆142Updated this week