xiaoan109 / ysyx-workbenchLinks
一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
☆22Updated 10 months ago
Alternatives and similar repositories for ysyx-workbench
Users that are interested in ysyx-workbench are comparing it to the libraries listed below
Sorting:
- ☆89Updated last month
- ☆67Updated last year
- ☆86Updated this week
- ☆70Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆64Updated 3 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆186Updated last year
- RISC-V 64 CPU☆10Updated last month
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- ☆68Updated 9 months ago
- Pick your favorite language to verify your chip.☆72Updated this week
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆214Updated 5 months ago
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 5 months ago
- A Study of the SiFive Inclusive L2 Cache☆69Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆145Updated last year
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Updated 6 years ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 7 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆176Updated 4 years ago
- CQU Dual Issue Machine☆37Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 5 years ago
- ☆156Updated last week
- Modern co-simulation framework for RISC-V CPUs☆159Updated last week
- CPU Design Based on RISCV ISA☆122Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 7 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- 一生一芯项目☆16Updated 2 years ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆45Updated 2 weeks ago