xiaoan109 / ysyx-workbenchLinks
一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
☆22Updated 10 months ago
Alternatives and similar repositories for ysyx-workbench
Users that are interested in ysyx-workbench are comparing it to the libraries listed below
Sorting:
- ☆89Updated 2 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- RISC-V 64 CPU☆10Updated 2 months ago
- ☆64Updated 3 years ago
- ☆67Updated last year
- ☆71Updated 2 years ago
- ☆86Updated 3 weeks ago
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 6 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆180Updated 4 years ago
- ☆68Updated 9 months ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Updated 6 years ago
- CQU Dual Issue Machine☆38Updated last year
- Pick your favorite language to verify your chip.☆74Updated 3 weeks ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆19Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- A Study of the SiFive Inclusive L2 Cache☆69Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆188Updated last year
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- riscv32i-cpu☆18Updated 5 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated last year
- ☆32Updated 4 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆215Updated 2 weeks ago
- 一生一芯项目☆17Updated 2 years ago
- 一生一芯RISCV处理器核代码仓库(包括相关工具)☆15Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 6 years ago
- Modern co-simulation framework for RISC-V CPUs☆159Updated last week
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆45Updated 2 weeks ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆145Updated last year