Alternatives and similar repositories for ahb_course

Users that are interested in ahb_course are comparing it to the libraries listed below

• raiyyanfaisal09 / AHB_APB-RTL
  AHB-APB Bridge RTL Design
  ☆16Updated 7 years ago
• wudayemen / gen_apb_file
  ☆75Updated 4 years ago
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆31Updated 5 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆25Updated 7 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆71Updated 5 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆119Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆75Updated 5 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆35Updated 8 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆35Updated 9 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆56Updated 4 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆38Updated 5 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆58Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆124Updated 11 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆100Updated 2 years ago
• ForrestBlue / cortexm0ds
  ☆74Updated 10 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆136Updated 4 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆163Updated 3 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆61Updated 9 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆94Updated 3 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆93Updated 4 months ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆136Updated 8 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆109Updated last year
• zhouzaixin / arm_soc
  ☆14Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆85Updated 7 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 7 months ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆53Updated 10 years ago