fluctlight001 / Nova132Links
A classic five stage pipelined processor
☆13Updated last year
Alternatives and similar repositories for Nova132
Users that are interested in Nova132 are comparing it to the libraries listed below
Sorting:
- 适用于龙芯杯团队赛入门选手的应急cache模块☆31Updated last year
- ☆91Updated 2 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆50Updated last week
- ☆64Updated 3 years ago
- ☆67Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆89Updated last month
- "aura" my super-scalar O3 cpu core☆24Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 8 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆192Updated last year
- ☆64Updated 2 months ago
- ☆159Updated last week
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆146Updated last year
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Updated last year
- ☆68Updated 10 months ago
- Asymmetric dual issue in-order microprocessor.☆33Updated 6 years ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆41Updated 5 years ago
- Documentation for XiangShan Design☆37Updated 2 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- ☆32Updated 4 months ago
- ☆20Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Updated 10 months ago
- ☆36Updated 5 months ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆62Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- Pick your favorite language to verify your chip.☆74Updated last week
- ☆35Updated 2 years ago
- 一生一芯的信息发布和内容网站☆135Updated 2 years ago