Alternatives and similar repositories for 3d-ice:

Users that are interested in 3d-ice are comparing it to the libraries listed below

• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated last year
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆22Updated 3 years ago
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆10Updated 10 months ago
• uvahotspot / HotSpot
  HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
  ☆105Updated last year
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆61Updated 3 weeks ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆22Updated 2 months ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆39Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆61Updated 2 months ago
• bu-icsg / TAP-2.5D
  ☆27Updated 3 years ago
• vaughnbetz / COFFE
  ☆41Updated 6 months ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆45Updated 2 weeks ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated 2 weeks ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆32Updated this week
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆71Updated 3 years ago
• yhqiu16 / FDRA
  DRA+RISC-V Exploration Framework
  ☆16Updated last year
• Linger0 / SRAM-Compute-In-Memory
  A collection of research papers on SRAM-based compute-in-memory architectures.
  ☆28Updated last year
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆20Updated 11 months ago
• mec-UMN / HISIM
  HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…
  ☆33Updated 2 weeks ago
• booniebears / CoMN
  ☆16Updated 11 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆48Updated last week
• nanocad-lab / CATCH
  CATCH 1.0, Initial full release of CATCH cost model.
  ☆13Updated last month
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆51Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆51Updated last month
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆59Updated last month
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆48Updated 3 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆13Updated 4 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆97Updated 4 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 3 years ago
• gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
  A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
  ☆21Updated 9 months ago