srivatsankrishnan / oss-arch-gymLinks
Open source version of ArchGym project.
☆114Updated last month
Alternatives and similar repositories for oss-arch-gym
Users that are interested in oss-arch-gym are comparing it to the libraries listed below
Sorting:
- ☆57Updated last month
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- A survey on Hardware Accelerated LLMs☆52Updated 4 months ago
- Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization☆30Updated 6 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆50Updated 3 weeks ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆66Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆53Updated 2 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- ☆91Updated last year
- ☆53Updated 2 months ago
- EQueue Dialect☆40Updated 3 years ago
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆27Updated this week
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆26Updated last year
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆96Updated last month
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆109Updated 2 years ago
- ☆30Updated 3 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆46Updated 2 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆87Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆80Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆150Updated 2 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 2 weeks ago
- ☆59Updated last week
- ☆99Updated this week
- ☆37Updated 3 years ago