MLNetwork / rostamLinks
☆24Updated 4 years ago
Alternatives and similar repositories for rostam
Users that are interested in rostam are comparing it to the libraries listed below
Sorting:
- Repository for MLCommons Chakra schema and tools☆39Updated last year
- HW/SW co-designed end-host RPC stack☆20Updated 3 years ago
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆11Updated 7 months ago
- A Cycle-level simulator for M2NDP☆28Updated 2 months ago
- ☆65Updated 4 years ago
- ☆19Updated 8 months ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆53Updated 11 months ago
- ☆14Updated last year
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆129Updated last year
- A Programmable Hardware Architecture for Network Transport Logic☆35Updated 3 years ago
- Clio, ASPLOS'22.☆77Updated 3 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- ☆19Updated 4 years ago
- C++/MPI proxies for distributed training of deep neural networks.☆13Updated 3 years ago
- Pin based tool for simulation of rack-scale disaggregated memory systems☆22Updated 4 months ago
- An Agile Chisel-Based SoC Design Framework☆27Updated 3 years ago
- Sharing the codebase and steps for artifact evaluation for ISCA 2023 paper☆14Updated last year
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago
- (elastic) cuckoo hashing☆14Updated 5 years ago
- ☆75Updated 4 years ago
- TACOS: [T]opology-[A]ware [Co]llective Algorithm [S]ynthesizer for Distributed Machine Learning☆25Updated last month
- This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memo…☆46Updated 8 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- ☆26Updated 2 years ago
- ☆14Updated 2 years ago
- ☆10Updated last year
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆103Updated 2 years ago
- Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour☆14Updated 6 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- ☆24Updated 2 years ago