Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
☆180Jan 24, 2024Updated 2 years ago
Alternatives and similar repositories for ethernet_mac
Users that are interested in ethernet_mac are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 5 years ago
- A VHDL implementation of an Ethernet MAC☆17Aug 13, 2012Updated 13 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆77Jan 29, 2017Updated 9 years ago
- SGMII☆14Jul 17, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog Ethernet components for FPGA implementation☆3,008Feb 27, 2025Updated last year
- A huge VHDL library for FPGA and digital ASIC development☆467Updated this week
- Ethernet 10GE MAC☆47Jul 17, 2014Updated 11 years ago
- Network Tap based on the ZedBoard and Ethernet FMC☆15Jun 23, 2026Updated last week
- Wishbone to AXI bridge (VHDL)☆49Aug 29, 2019Updated 6 years ago
- UART to AXI Stream interface written in VHDL☆19Oct 20, 2022Updated 3 years ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆21May 19, 2026Updated last month
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆68Mar 15, 2022Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 9 years ago
- Network protocol libraries for VHDL test benches☆13Mar 9, 2026Updated 3 months ago
- 10Gb Ethernet Switch☆266Jun 26, 2026Updated last week
- Flexible VHDL library☆197Jun 28, 2023Updated 3 years ago
- Playing around with Formal Verification of Verilog and VHDL☆65Feb 22, 2021Updated 5 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆88Oct 2, 2019Updated 6 years ago
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆36Jun 2, 2026Updated last month
- VHDL I2S transmitter☆16Oct 29, 2018Updated 7 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated last month
- Verilog RTL Design☆50Sep 4, 2021Updated 4 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- ☆12Apr 3, 2017Updated 9 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆935Apr 15, 2026Updated 2 months ago
- Connecting FPGA and MCU using Ethernet RMII☆23Jan 23, 2016Updated 10 years ago
- Wishbone SATA Controller☆26Jun 23, 2026Updated last week
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆606Jul 30, 2025Updated 11 months ago
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆17Jul 11, 2015Updated 10 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆42Apr 28, 2026Updated 2 months ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆19Oct 23, 2023Updated 2 years ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 3 months ago
- bootgen source code☆62Jun 14, 2026Updated 2 weeks ago
- ☆90May 4, 2017Updated 9 years ago