Alternatives and similar repositories for ethernet_mac

Users that are interested in ethernet_mac are comparing it to the libraries listed below

• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆170Updated 3 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆236Updated 3 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆193Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆253Updated last year
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆244Updated last month
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆197Updated last week
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆266Updated 2 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆130Updated 8 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆160Updated 11 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆323Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆450Updated this week
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆70Updated 2 months ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆202Updated 7 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆97Updated 5 years ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 3 years ago
• hypernyan / eth_vlg
  ☆78Updated 4 years ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆266Updated 6 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆285Updated last year
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
  ☆132Updated last week
• xesscorp / VHDL_Lib
  Library of VHDL components that are useful in larger designs.
  ☆242Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆129Updated 8 months ago
• Avnet / hdl
  ☆114Updated 10 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆172Updated 2 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago