Alternatives and similar repositories for ethernet_mac

Users that are interested in ethernet_mac are comparing it to the libraries listed below

• CospanDesign / nysa-sata
  ☆85Updated 8 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆306Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆232Updated 2 years ago
• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆101Updated 6 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆217Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆250Updated 6 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆125Updated 2 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆134Updated 10 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆187Updated 2 years ago
• hypernyan / eth_vlg
  ☆70Updated 3 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆118Updated last month
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 6 months ago
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆242Updated last year
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• HDLForBeginners / Examples
  ☆95Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• Avnet / hdl
  ☆113Updated 3 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆172Updated 2 weeks ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆194Updated 6 years ago
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆249Updated this week
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆64Updated 8 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆256Updated 6 months ago
• jamieiles / uart
  Verilog UART
  ☆173Updated 12 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆151Updated 4 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year