yol / ethernet_macLinks
Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
☆175Updated last year
Alternatives and similar repositories for ethernet_mac
Users that are interested in ethernet_mac are comparing it to the libraries listed below
Sorting:
- Flexible VHDL library☆191Updated 2 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- Verilog digital signal processing components☆162Updated 3 years ago
- Verilog wishbone components☆123Updated last year
- Control and Status Register map generator for HDL projects☆128Updated 7 months ago
- ☆89Updated 8 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆192Updated 2 weeks ago
- A configurable C++ generator of pipelined Verilog FFT cores☆251Updated last year
- A simple, basic, formally verified UART controller☆319Updated last year
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆159Updated 10 months ago
- A huge VHDL library for FPGA and digital ASIC development☆417Updated last week
- ☆76Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆115Updated last year
- USB3 PIPE interface for Xilinx 7-Series☆239Updated 3 years ago
- FuseSoC standard core library☆151Updated 2 weeks ago
- Vivado build system☆69Updated 2 weeks ago
- Example designs for FPGA Drive FMC☆282Updated 11 months ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆200Updated 7 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 3 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- ☆114Updated 2 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated last week
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆263Updated 6 years ago
- HDL symbol generator☆200Updated 2 years ago
- Fixed Point Math Library for Verilog☆145Updated 11 years ago
- A series of CORDIC related projects☆120Updated last year
- ☆137Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago