Alternatives and similar repositories for keyboard-ip

Users that are interested in keyboard-ip are comparing it to the libraries listed below

• krabo0om / pauloBlaze
  A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.
  ☆22Updated 4 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆14Updated this week
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 5 years ago
• martinjthompson / libv
  Useful set of library functions for VHDL
  ☆47Updated 12 years ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 3 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆14Updated 7 years ago
• juliancoy / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆15Updated 3 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆18Updated 3 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆34Updated 3 months ago
• warclab / idea
  iDEA FPGA Soft Processor
  ☆16Updated 9 years ago
• jherkenhoff / Bitmap-VHDL-Package
  A vhdl package for reading and writing bitmap files.
  ☆11Updated 8 years ago
• MJoergen / Avalon
  Utilities for Avalon Memory Map
  ☆11Updated last year
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 12 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• ObKo / USBCore
  USB Full-Speed/Hi-Speed Device Controller core for FPGA
  ☆32Updated 5 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆32Updated 5 years ago
• lnls-dig / general-cores
  general-cores
  ☆21Updated 6 months ago
• krtkl / snickerdoodle-hls-data-mover
  A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…
  ☆16Updated 7 years ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆46Updated 5 years ago
• codeshaa / 16-bit-HDLC-using-VHDL
  High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
  ☆29Updated 9 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• campera-es / ces_util_lib
  CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules
  ☆11Updated 4 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 11 months ago
• suoto / fpga_cores
  ☆33Updated 2 years ago