jsyk / miilinkLinks
Connecting FPGA and MCU using Ethernet RMII
☆23Updated 9 years ago
Alternatives and similar repositories for miilink
Users that are interested in miilink are comparing it to the libraries listed below
Sorting:
- USB Full Speed PHY☆45Updated 5 years ago
- Dockerized FPGA toolchain experiments☆29Updated last year
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- USB serial device (CDC-ACM)☆40Updated 5 years ago
- artix-7 PCIe dev board☆29Updated 7 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆31Updated 2 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 6 months ago
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- ☆45Updated 2 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆56Updated 2 years ago
- Small footprint and configurable JESD204B core☆45Updated 2 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Wishbone controlled I2C controllers☆51Updated 8 months ago
- Generic Logic Interfacing Project☆46Updated 5 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆95Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Digital FM Radio Receiver for FPGA☆61Updated 9 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆44Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆21Updated 2 years ago
- an sata controller using smallest resource.☆16Updated 11 years ago
- Eclipse based IDE for RISC-V bare metal software development.☆19Updated 5 years ago
- Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM☆37Updated last year
- Xilinx virtual cable server for generic FTDI 4232H.☆58Updated last year
- JESD204b modules in VHDL☆30Updated 6 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 11 years ago