ZipCPU / zipversa
A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
☆13Updated 5 years ago
Alternatives and similar repositories for zipversa:
Users that are interested in zipversa are comparing it to the libraries listed below
- A bit-serial CPU☆18Updated 5 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- USB 1.1 Device IP Core☆20Updated 7 years ago
- CMod-S6 SoC☆40Updated 7 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- Open Processor Architecture☆26Updated 8 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 3 months ago
- Small footprint and configurable Inter-Chip communication cores☆56Updated last month
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 2 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆30Updated 4 years ago
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- GUI for SymbiYosys☆13Updated last year
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated last week
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆17Updated 4 months ago
- IRSIM switch-level simulator for digital circuits☆32Updated 10 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 2 weeks ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- SPI core☆15Updated 5 years ago
- Finding the bacteria in rotting FPGA designs.☆13Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago