Alternatives and similar repositories for zipversa

Users that are interested in zipversa are comparing it to the libraries listed below

• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆43Updated 7 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated this week
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆41Updated 9 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• ZipCPU / wbspi
  A collection of SPI related cores
  ☆20Updated last year
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 10 months ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• mmicko / enigmaFPGA
  Enigma in FPGA
  ☆29Updated 6 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• olofk / simple_spi
  SPI core
  ☆14Updated 6 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 7 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆30Updated last week
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆51Updated 7 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆48Updated last week
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆54Updated 4 years ago