ZipCPU / zipversaLinks
A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
☆16Updated 5 years ago
Alternatives and similar repositories for zipversa
Users that are interested in zipversa are comparing it to the libraries listed below
Sorting:
- A Verilog Synthesis Regression Test☆37Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- A bit-serial CPU☆19Updated 5 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Open Processor Architecture☆26Updated 9 years ago
- RISC-V processor☆31Updated 3 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 8 months ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆55Updated last year
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- SPI core☆14Updated 5 years ago
- A collection of SPI related cores☆17Updated 9 months ago
- VexRiscv-SMP integration test with LiteX.☆25Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated last month
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆19Updated 12 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆36Updated 3 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 6 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 7 months ago
- A reimplementation of a tiny stack CPU☆85Updated last year
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆11Updated 6 years ago