alknvl / axis_udpLinks
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
☆62Updated 3 years ago
Alternatives and similar repositories for axis_udp
Users that are interested in axis_udp are comparing it to the libraries listed below
Sorting:
- ☆79Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆86Updated last year
- Implementation of the PCIe physical layer☆56Updated 4 months ago
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated 3 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- AXI Interconnect☆54Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆49Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆143Updated 2 years ago
- ☆26Updated 4 months ago
- ☆31Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆158Updated 8 months ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- ☆38Updated 10 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆33Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆45Updated 2 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆24Updated 2 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆15Updated 3 years ago
- Ethernet interface modules for Cocotb☆71Updated 2 months ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago