Network protocol libraries for VHDL test benches
☆13Mar 9, 2026Updated 2 weeks ago
Alternatives and similar repositories for netwiz
Users that are interested in netwiz are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Apr 10, 2025Updated 11 months ago
- ☆16Sep 14, 2023Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.☆17Nov 12, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 记录自己日常学习工程中所涉及到的一些电力电子变换器相关的仿真和设计原档。☆14Jun 10, 2022Updated 3 years ago
- C++ realization of IEC-60870-5-104 for LPC1768+FreeRTOS+lwIP☆13Apr 29, 2015Updated 10 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 4 months ago
- STM32 PIL example in Simulink☆15Apr 19, 2018Updated 7 years ago
- Interface definitions for VHDL-2019.☆34Mar 1, 2026Updated 3 weeks ago
- A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the A…☆13Aug 18, 2025Updated 7 months ago
- 基于MATLAB&Simulink的无感pmsm的FOC算法模型，支持仿真和实验☆20Sep 23, 2024Updated last year
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆72Feb 12, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Userspace I/O library for Xilinx AXI S2MM DMA☆11Sep 9, 2025Updated 6 months ago
- Small example demonstrating overlay windows with accessibility service on Android.☆10Apr 22, 2021Updated 4 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 4 months ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 4 years ago
- Retro motherboard BIOS modifications released on TheRetroWeb☆16Nov 8, 2025Updated 4 months ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- Capture data from multiple ADCs concurrently using an FPGA. Stream the captured data out over ethernet + UDP. Tested on the Spartan 6 XC6…☆17Dec 10, 2016Updated 9 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A software-based small signal analysis tool for digital controlled power supplies and more☆18May 2, 2023Updated 2 years ago
- Website!☆10Aug 29, 2020Updated 5 years ago
- Openhardware educational platform based on the ideas of the ulx3s and Gecko4Education☆16Jul 16, 2025Updated 8 months ago
- High-througput logic analyzer for FPGA☆16Oct 8, 2020Updated 5 years ago
- ☆11Jan 6, 2022Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Feb 16, 2026Updated last month
- HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and aut…☆36Oct 28, 2024Updated last year
- A software development toolkit for signal processing which uses blocks☆15Feb 11, 2026Updated last month
- VHDL PCIe Transceiver☆32Jul 2, 2020Updated 5 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Mirror of the now discontinued ORCA RISC-V processor from VectorBlox.☆10Feb 11, 2020Updated 6 years ago
- MATLAB-based FIR filter and profile designer☆10Jan 25, 2017Updated 9 years ago
- Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.☆13May 28, 2015Updated 10 years ago
- design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog☆10Sep 26, 2022Updated 3 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- LightWeight IP Application Examples for Xilinx FPGA☆15Jan 19, 2016Updated 10 years ago