CRAFT-THU / XB-SimLinks
A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
☆34Updated 3 years ago
Alternatives and similar repositories for XB-Sim
Users that are interested in XB-Sim are comparing it to the libraries listed below
Sorting:
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆43Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- ☆71Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆52Updated 4 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- ☆35Updated 5 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆41Updated 5 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆58Updated last week
- ☆37Updated 5 months ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆24Updated 8 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 4 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆12Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- ☆41Updated last year
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- ☆72Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- ☆34Updated 6 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago