CospanDesign / sdio-deviceLinks
☆19Updated 7 years ago
Alternatives and similar repositories for sdio-device
Users that are interested in sdio-device are comparing it to the libraries listed below
Sorting:
- SDIO Device Verilog Core☆22Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆61Updated 2 years ago
- turbo 8051☆29Updated 8 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆27Updated 3 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆25Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 3 weeks ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆25Updated 6 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- AGM bitstream utilities and decoded files from Supra☆46Updated 3 months ago
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆44Updated 4 years ago
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Updated last year
- A configurable USB 2.0 device core☆32Updated 5 years ago
- A RISC-V processor☆15Updated 6 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- MIPI DSI transmitter core for Xilinx FPGAs (work in progress)☆85Updated 8 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆50Updated 11 years ago
- Wishbone controlled I2C controllers☆53Updated last year