CospanDesign / sdio-deviceLinks
☆19Updated 7 years ago
Alternatives and similar repositories for sdio-device
Users that are interested in sdio-device are comparing it to the libraries listed below
Sorting:
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆31Updated 4 years ago
- SDIO Device Verilog Core☆24Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆26Updated 3 years ago
- turbo 8051☆29Updated 8 years ago
- AGM bitstream utilities and decoded files from Supra☆48Updated 5 months ago
- Mini CPU design with JTAG UART support☆21Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 3 weeks ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- MIPI DSI transmitter core for Xilinx FPGAs (work in progress)☆86Updated 8 years ago
- Minimal DVI / HDMI Framebuffer☆84Updated 5 years ago
- USB serial device (CDC-ACM)☆44Updated 5 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 4 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆26Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Updated 5 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆41Updated last year
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Yet another free 8051 FPGA core☆36Updated 7 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Updated 7 years ago