daveshah1 / ElasticC

Related projects ⓘ

Alternatives and complementary repositories for ElasticC

• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆13Updated 3 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆79Updated 3 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 11 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆20Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆10Updated 2 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆36Updated last year
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆28Updated 7 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last month
• whitequark / Yumewatari
  妖刀夢渡
  ☆56Updated 5 years ago
• peteut / migen-axi
  AXI support for Migen/MiSoC
  ☆25Updated 4 months ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 2 years ago
• knielsen / ice40_viewer
  ☆58Updated last year
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆20Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆40Updated 7 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 8 months ago
• daveshah1 / nextpnr
  nextpnr portable FPGA place and route tool
  ☆12Updated 3 years ago
• rodrigomelo9 / verifying-foss-hdl-synthesizers
  a project to check the FOSS synthesizers against vendors EDA tools
  ☆12Updated 4 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆26Updated last month
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago