daveshah1 / ElasticC
lightweight open HLS for FPGA rapid prototyping
☆20Updated 7 years ago
Alternatives and similar repositories for ElasticC:
Users that are interested in ElasticC are comparing it to the libraries listed below
- Small footprint and configurable HyperBus core☆11Updated 2 years ago
- Industry standard I/O for nMigen☆12Updated 5 years ago
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Verilog based simulation modell for 7 Series PLL☆13Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Misc open FPGA flow examples☆8Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 3 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- A padring generator for ASICs☆25Updated last year
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Small footprint and configurable JESD204B core☆42Updated 2 weeks ago
- A configurable USB 2.0 device core☆31Updated 4 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆32Updated 5 months ago
- AXI support for Migen/MiSoC☆27Updated last week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- 妖刀夢渡☆59Updated 6 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Yosys Plugins☆21Updated 5 years ago
- Cross compile FPGA tools☆22Updated 4 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆40Updated this week
- OpenFPGA☆33Updated 7 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆12Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆11Updated 6 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Updated 4 years ago
- PicoRV☆44Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago