Alternatives and similar repositories for ElasticC

Users that are interested in ElasticC are comparing it to the libraries listed below

• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 11 months ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆63Updated 6 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆14Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated this week
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 4 years ago
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated last year
• xobs / coriolis
  An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.
  ☆10Updated 7 years ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆17Updated 5 years ago
• kbeckmann / pergola_projects
  My pergola FPGA projects
  ☆30Updated 4 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆21Updated 4 years ago
• m-labs / nmigen-stdio
  Industry standard I/O for nMigen
  ☆12Updated 5 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• peteut / migen-axi
  AXI support for Migen/MiSoC
  ☆28Updated 6 months ago
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 6 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆102Updated 2 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 7 years ago
• nmi-leipzig / sim-x-pll
  Verilog based simulation modell for 7 Series PLL
  ☆17Updated 5 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 8 years ago
• hedgeberg / VerilogCommon
  A repo of basic Verilog/SystemVerilog modules useful in other circuits.
  ☆21Updated 8 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago