Alternatives and similar repositories for fphdl

Users that are interested in fphdl are comparing it to the libraries listed below

• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated this week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆62Updated 3 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆74Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆130Updated 8 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆65Updated 4 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆75Updated last week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated this week
• kevinpt / symbolator
  HDL symbol generator
  ☆201Updated 3 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆27Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 4 months ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆193Updated 2 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated last month
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆74Updated 4 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆60Updated last week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆75Updated last week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆52Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 11 months ago
• olofk / ipyxact
  Python-based IP-XACT parser and utilities
  ☆143Updated last year
• ldoolitt / vhd2vl
  ☆139Updated 3 weeks ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆61Updated 3 weeks ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago