wavedrom / vcdromLinks
VCD viewer
☆98Updated 4 months ago
Alternatives and similar repositories for vcdrom
Users that are interested in vcdrom are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆65Updated 2 months ago
- impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…☆29Updated last month
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- HTML & Js based VCD viewer☆66Updated this week
- SystemVerilog synthesis tool☆223Updated 9 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆63Updated last month
- RISC-V Nox core☆71Updated 5 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated last week
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- FuseSoC standard core library☆151Updated last month
- Experimental flows using nextpnr for Xilinx devices☆252Updated last year
- Python package for writing Value Change Dump (VCD) files.☆128Updated last year
- Re-coded Xilinx primitives for Verilator use☆51Updated 6 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- ☆88Updated 2 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆106Updated this week
- WAL enables programmable waveform analysis.☆163Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- Naive Educational RISC V processor☆94Updated 2 months ago
- The specification for the FIRRTL language☆62Updated last month
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆146Updated 2 years ago
- D3.js based wave (signal) visualizer☆67Updated 4 months ago
- RISC-V Verification Interface☆134Updated 3 weeks ago
- A SystemVerilog source file pickler.☆60Updated last year
- Waveform Viewer Extension for VScode☆300Updated last week
- WaveDrom compatible python command line☆112Updated 2 years ago