wavedrom / vcdromLinks
VCD viewer
☆97Updated 2 months ago
Alternatives and similar repositories for vcdrom
Users that are interested in vcdrom are comparing it to the libraries listed below
Sorting:
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- D3.js based wave (signal) visualizer☆64Updated 2 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆63Updated 2 weeks ago
- RISC-V Nox core☆68Updated 3 months ago
- Naive Educational RISC V processor☆91Updated 3 weeks ago
- impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…☆29Updated last month
- HTML & Js based VCD viewer☆65Updated 3 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- SystemVerilog synthesis tool☆216Updated 7 months ago
- ☆99Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆160Updated 3 weeks ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆98Updated last week
- Re-coded Xilinx primitives for Verilator use☆50Updated 4 months ago
- WaveDrom compatible python command line☆109Updated 2 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆84Updated this week
- RISC-V System on Chip Template☆159Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆187Updated this week
- FuseSoC standard core library☆147Updated 5 months ago
- ☆85Updated 3 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- Experimental flows using nextpnr for Xilinx devices☆246Updated last year
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆65Updated last month
- A SystemVerilog source file pickler.☆60Updated last year
- WAL enables programmable waveform analysis.☆160Updated last week
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 3 weeks ago