Alternatives and similar repositories for vcdrom

Users that are interested in vcdrom are comparing it to the libraries listed below

• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆82Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 3 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated this week
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆292Updated this week
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated last week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆248Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 3 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆127Updated 6 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆144Updated 2 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆65Updated last month
• toem / impulse.vscode
  impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…
  ☆29Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆127Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆92Updated 2 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆190Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆103Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆129Updated this week
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆111Updated 2 years ago
• pieter3d / simview
  ☆88Updated 2 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆86Updated this week
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆188Updated 2 months ago
• aignacio / nox
  RISC-V Nox core
  ☆69Updated 4 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆156Updated last week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆279Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆162Updated last month