wavedrom / vcdromLinks
VCD viewer
☆92Updated last week
Alternatives and similar repositories for vcdrom
Users that are interested in vcdrom are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆122Updated 2 months ago
- SystemVerilog synthesis tool☆201Updated 4 months ago
- D3.js based wave (signal) visualizer☆63Updated last year
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated 9 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆60Updated last month
- Re-coded Xilinx primitives for Verilator use☆50Updated 3 weeks ago
- HTML & Js based VCD viewer☆61Updated last week
- ☆79Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- FuseSoC standard core library☆144Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- ☆96Updated last year
- Experimental flows using nextpnr for Xilinx devices☆244Updated 9 months ago
- RISC-V Nox core☆65Updated 3 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- FPGA tool performance profiling☆102Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…☆28Updated 3 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- A SystemVerilog source file pickler.☆59Updated 8 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Python package for writing Value Change Dump (VCD) files.☆120Updated 8 months ago
- Naive Educational RISC V processor☆84Updated last month
- VCD file (Value Change Dump) command line viewer☆119Updated 2 years ago
- SystemVerilog frontend for Yosys☆135Updated last week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago