Alternatives and similar repositories for gvi

Users that are interested in gvi are comparing it to the libraries listed below

• VHDL / news
  VHDL related news.
  ☆26Updated this week
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆28Updated 3 months ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated 2 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 9 months ago
• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 3 years ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆39Updated 3 weeks ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 4 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆75Updated last week
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 8 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆56Updated 3 months ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆15Updated 5 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated this week
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• suoto / fpga_cores
  ☆33Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆63Updated 4 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆30Updated 9 months ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆35Updated 8 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago