Alternatives and similar repositories for gvi

Users that are interested in gvi are comparing it to the libraries listed below

• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆30Updated 4 months ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated last year
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆12Updated 2 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆53Updated 2 weeks ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 5 years ago
• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 3 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆12Updated last month
• wzab / agwb
  Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
  ☆12Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 5 years ago
• UVVM / UVVM_Light
  This repository is a subset of UVVM with Utility library and BFMs, and is intended as a UVVM starting platform for thos who only need the…
  ☆21Updated 9 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last month
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• OSVVM / VerificationIP
  Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.
  ☆10Updated 4 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 8 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆58Updated 4 years ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆12Updated this week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• schang412 / cocotbext-spi
  ☆21Updated last month
• wallento / cocotbext-wishbone
  ☆13Updated 5 months ago