kunalg123 / sky130RTLDesignAndSynthesisWorkshopLinks
☆19Updated 3 years ago
Alternatives and similar repositories for sky130RTLDesignAndSynthesisWorkshop
Users that are interested in sky130RTLDesignAndSynthesisWorkshop are comparing it to the libraries listed below
Sorting:
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆77Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- ☆43Updated 3 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆44Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆118Updated 4 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated 2 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- ☆17Updated 2 years ago
- ☆15Updated 4 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- ☆37Updated 6 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Simple single-port AXI memory interface☆48Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year