☆56May 28, 2023Updated 3 years ago
Alternatives and similar repositories for intel-training-modules
Users that are interested in intel-training-modules are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆14Apr 29, 2024Updated 2 years ago
- Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically f…☆124Jul 17, 2023Updated 3 years ago
- LED blink example design for the Arrow DECA FPGA board☆16Jul 30, 2021Updated 5 years ago
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆14Apr 1, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆17Sep 5, 2025Updated 11 months ago
- ☆12Sep 18, 2024Updated last year
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year
- ☆125Nov 30, 2025Updated 8 months ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 4 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 8 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆22Jul 28, 2026Updated 2 weeks ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆27Feb 26, 2021Updated 5 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 9 years ago
- Reticle evaluation (PLDI 2021)☆12Apr 12, 2021Updated 5 years ago
- VUnit GitHub action☆19May 23, 2021Updated 5 years ago
- ☆19Oct 5, 2020Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆63Dec 31, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated 7 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆43Sep 22, 2025Updated 10 months ago
- ☆47Apr 1, 2026Updated 4 months ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- Updated version of the XUP Workshops☆13Aug 10, 2018Updated 8 years ago
- Examples illustrating usage of the rocBLAS library☆17Aug 12, 2024Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- A Verilog RTL model of a simple 8-bit RISC processor☆20Jan 15, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Audio filtering with pyfda and cocotb☆13Sep 24, 2020Updated 5 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- HDLRegression: Simple, efficient, Python3-based FPGA regression test runner. Streamline the verification workflow.☆31Apr 16, 2026Updated 3 months ago
- A simple Emacs minor mode for VUnit☆12Jul 14, 2025Updated last year
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆30Jul 1, 2026Updated last month
- Example SystemVerilog UVM Environment☆11Jun 23, 2015Updated 11 years ago
- Open Programmable Acceleration Engine☆270Jul 10, 2026Updated last month