ARC-Lab-UF / intel-training-modulesLinks
☆46Updated 2 years ago
Alternatives and similar repositories for intel-training-modules
Users that are interested in intel-training-modules are comparing it to the libraries listed below
Sorting:
- SystemVerilog Tutorial☆191Updated 2 months ago
- ☆175Updated 3 years ago
- ☆113Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- A Fast, Low-Overhead On-chip Network☆267Updated last week
- Altera Advanced Synthesis Cookbook 11.0☆112Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- A demo system for Ibex including debug support and some peripherals☆84Updated 2 weeks ago
- Verilog/SystemVerilog Guide☆80Updated 2 years ago
- ☆60Updated 9 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- Network on Chip Implementation written in SytemVerilog☆198Updated 3 years ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- A collection of commonly asked RTL design interview questions☆38Updated 8 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆119Updated 4 months ago
- ☆114Updated last year
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆74Updated 4 months ago
- An overview of TL-Verilog resources and projects☆82Updated last month
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆133Updated 2 years ago
- PCI express simulation framework for Cocotb☆192Updated 5 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆22Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆137Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Unit testing for cocotb☆166Updated 2 months ago
- Verilog Configurable Cache☆192Updated last week
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago