ARC-Lab-UF / intel-training-modules
☆40Updated last year
Alternatives and similar repositories for intel-training-modules:
Users that are interested in intel-training-modules are comparing it to the libraries listed below
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆54Updated 10 months ago
- A demo system for Ibex including debug support and some peripherals☆61Updated 5 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆37Updated 2 years ago
- ☆70Updated 5 months ago
- ☆45Updated 8 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆159Updated 2 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- ☆86Updated last year
- ☆130Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago
- Introductory course into static timing analysis (STA).☆83Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated last month
- ☆70Updated 10 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆49Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆75Updated 10 months ago
- SystemVerilog Tutorial☆123Updated this week
- A Fast, Low-Overhead On-chip Network☆165Updated this week
- AXI4 and AXI4-Lite interface definitions☆91Updated 4 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆108Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆116Updated 4 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆13Updated last year
- Python Tool for UVM Testbench Generation☆50Updated 8 months ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- SystemVerilog modules and classes commonly used for verification☆45Updated last month
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year