intel / aji_openocdLinks
A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the ARM HPS. It will be relaxed in future release. Requires libaji_client (https://github.com/intel/libaji_client).
☆13Updated 5 months ago
Alternatives and similar repositories for aji_openocd
Users that are interested in aji_openocd are comparing it to the libraries listed below
Sorting:
- This is the client side library to access JTAG Server distributed with Quartus (jtagd/jtagserver.exe). The protocol is known as Advanced …☆20Updated 5 months ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Updated 4 years ago
- An FPGA/PCI Device Reference Platform☆32Updated 5 years ago
- JTAG Hardware Abstraction Library☆37Updated 2 years ago
- Container for compiling LiteX HDL FPGA designs using the free OpenXC7 tool chain and GitHub code spaces☆27Updated 2 years ago
- Test of a RP2040 PMOD attached to a LiteX SoC.☆28Updated 2 years ago
- Bit streams forthe Ulx3s ECP5 device☆18Updated 2 years ago
- Tool for decoding mask programmed PLAs from die shots☆22Updated 5 years ago
- ☆54Updated 3 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆70Updated last week
- Use ECP5 JTAG port to interact with user design☆33Updated 4 years ago
- understanding the tinyfpga bootloader☆25Updated 7 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆20Updated 3 years ago
- KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specifica…☆43Updated 4 years ago
- PCIe analyzer experiments☆65Updated 5 years ago
- VexRiscV system with GDB-Server in Hardware☆21Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 4 years ago
- Exploring gate level simulation☆58Updated 9 months ago
- 妖刀夢渡☆63Updated 6 years ago
- open-source logic analyzer for FPGAs☆101Updated 7 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆58Updated 2 years ago
- ice40 USB Analyzer☆57Updated 5 years ago
- 360nosc0pe Siglent SDS 1x0xX-E FPGA bitstreams☆17Updated 7 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- FPGA USB stack written in LiteX☆132Updated 3 years ago
- Tiny tips for Colorlight i5 FPGA board☆65Updated 4 years ago
- An FPGA reverse engineering and documentation project☆65Updated this week
- Siglent SDS1x0xX-E FPGA bitstreams☆45Updated last year
- ☆44Updated 10 months ago
- Miscellaneous ULX3S examples (advanced)☆82Updated 7 months ago