samkaufman / morelloLinks
☆13Updated this week
Alternatives and similar repositories for morello
Users that are interested in morello are comparing it to the libraries listed below
Sorting:
- IREE compiler and runtime for Snitch☆14Updated last month
- HeteroCL-MLIR dialect for accelerator design☆41Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆117Updated 2 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated 5 months ago
- The missing pieces (as far as boilerplate reduction goes) of the upstream MLIR python bindings.☆111Updated last month
- A translation validation framework for MLIR☆89Updated 7 months ago
- ☆18Updated 3 weeks ago
- Time-sensitive affine types for predictable hardware generation☆146Updated last week
- ☆40Updated 4 years ago
- BTOR2 MLIR project☆26Updated last year
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆143Updated this week
- EQueue Dialect☆40Updated 3 years ago
- MLIR+EqSat☆18Updated 2 months ago
- Polyhedral High-Level Synthesis in MLIR☆34Updated 2 years ago
- An out-of-tree MLIR dialect template.☆110Updated last year
- FPGA synthesis tool powered by program synthesis☆52Updated last month
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- A Hardware Pipeline Description Language☆49Updated 3 months ago
- ☆22Updated 8 months ago
- ☆40Updated last month
- ☆59Updated 2 years ago
- ☆16Updated 3 months ago
- Data-Centric MLIR dialect☆43Updated 2 years ago
- A Specification and a Library for Data Exchange in Polyhedral Compilation Tools☆32Updated last year
- A unified programming framework for high and portable performance across FPGAs and GPUs☆11Updated 7 months ago
- ☆114Updated last week
- Re-implementation of the TASO compiler using equality saturation☆135Updated 4 years ago
- High level synthesis language for hardware design☆62Updated this week
- Asynchronous semantics for architectural simulation and synthesis.☆55Updated this week