CMU-SAFARI / SoftMCLinks
SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https:/…
☆134Updated last year
Alternatives and similar repositories for SoftMC
Users that are interested in SoftMC are comparing it to the libraries listed below
Sorting:
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆85Updated 9 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Fast and accurate DRAM power and energy estimation tool☆165Updated last week
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated last year
- ☆81Updated last year
- Comment on the rocket-chip source code☆179Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆115Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆187Updated 4 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆110Updated last week
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆71Updated 9 months ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆36Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 4 years ago
- A wrapper for the SPEC CPU2006 benchmark suite.☆88Updated 4 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆95Updated 2 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆280Updated last month
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆237Updated 2 years ago
- RISC-V Torture Test☆196Updated 11 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 9 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated this week
- The official repository for the gem5 resources sources.☆72Updated last month
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆82Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆132Updated last week