SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https:/…
☆147Aug 24, 2023Updated 2 years ago
Alternatives and similar repositories for SoftMC
Users that are interested in SoftMC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Jun 20, 2020Updated 5 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆116Aug 10, 2025Updated 7 months ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆686Aug 29, 2023Updated 2 years ago
- ☆76Mar 7, 2026Updated 2 weeks ago
- Source code for testing the Row Hammer error mechanism in DRAM devices. Described in the ISCA 2014 paper by Kim et al. at http://users.ec…☆235Sep 2, 2015Updated 10 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomen…☆37Jan 11, 2024Updated 2 years ago
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆12May 17, 2024Updated last year
- BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…☆19Oct 9, 2020Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆72Dec 11, 2023Updated 2 years ago
- ☆24Apr 20, 2024Updated last year
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆12Feb 12, 2016Updated 10 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆17Nov 15, 2022Updated 3 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆60Sep 30, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆182Oct 1, 2022Updated 3 years ago
- FPGA-based DRAM tester supporting RDIMM DDR5 memories☆29Jan 29, 2026Updated last month
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆11Jan 23, 2026Updated 2 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆13May 15, 2020Updated 5 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆294Nov 11, 2020Updated 5 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Oct 9, 2020Updated 5 years ago
- This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memo…☆48Jun 2, 2017Updated 8 years ago
- This repository is for sharing code and information related to researching the "rowhammer" problem with respect to GPUs.☆15Apr 20, 2017Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Clio, ASPLOS'22.☆79Feb 8, 2022Updated 4 years ago
- MNSIM version 1.1. We have uploaded a high-level modeling tool and please use this version: https://github.com/Zhu-Zhenhua/MNSIM_Python☆12Dec 12, 2019Updated 6 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆517Feb 4, 2026Updated last month
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…☆169Apr 29, 2024Updated last year
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆12Jan 18, 2016Updated 10 years ago
- HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler…☆19Jan 11, 2016Updated 10 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆31Oct 23, 2023Updated 2 years ago
- TRRespass☆128May 5, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Source code of the simulator used in the Mosaic paper from MICRO 2017: "Mosaic: A GPU Memory Manager with Application-Transparent Support…☆50Aug 21, 2018Updated 7 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Feb 6, 2023Updated 3 years ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆214Apr 18, 2023Updated 2 years ago
- Tools and experiments for 0sim. Simulate system software behavior on machines with terabytes of main memory from your desktop.☆21May 27, 2020Updated 5 years ago
- This repository contains examples of DRAMA reverse-engineering and side-channel attacks☆194Aug 23, 2017Updated 8 years ago
- Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.☆196Dec 8, 2022Updated 3 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Jun 15, 2025Updated 9 months ago