CMU-SAFARI / SoftMC
SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https:/…
☆132Updated last year
Alternatives and similar repositories for SoftMC:
Users that are interested in SoftMC are comparing it to the libraries listed below
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- ☆81Updated last year
- Comment on the rocket-chip source code☆179Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆132Updated 2 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆77Updated 8 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆234Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆164Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆196Updated this week
- Fast and accurate DRAM power and energy estimation tool☆158Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆126Updated last week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆65Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆153Updated last year
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆63Updated 5 years ago
- gem5 Tips & Tricks☆68Updated 5 years ago
- RISC-V Torture Test☆193Updated 9 months ago
- An integrated CGRA design framework☆88Updated last month
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆35Updated 5 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆264Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- The official repository for the gem5 resources sources.☆67Updated 2 weeks ago
- DRAMSim2: A cycle accurate DRAM simulator☆270Updated 4 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆194Updated last month
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆184Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated 2 weeks ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆76Updated last year
- Chisel Learning Journey☆109Updated 2 years ago