CMU-SAFARI / SoftMC
SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https:/…
☆130Updated last year
Alternatives and similar repositories for SoftMC:
Users that are interested in SoftMC are comparing it to the libraries listed below
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆63Updated 5 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆228Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Fast and accurate DRAM power and energy estimation tool☆147Updated this week
- Comment on the rocket-chip source code☆170Updated 6 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆241Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- ☆77Updated 11 months ago
- The official repository for the gem5 resources sources.☆64Updated this week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆60Updated 7 months ago
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆113Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆166Updated 6 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- gem5 Tips & Tricks☆66Updated 4 years ago
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆72Updated 5 months ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆178Updated 4 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆140Updated last year
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆103Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year
- DRAMSim2: A cycle accurate DRAM simulator☆263Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆182Updated 2 months ago
- A wrapper for the SPEC CPU2006 benchmark suite.☆87Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 7 months ago
- ☆77Updated 2 years ago
- Heterogeneous simulator for DECADES Project☆31Updated 8 months ago