yvnr4you / AMBA_AXI3View external linksLinks
System Verilog and Emulation. Written all the five channels.
☆35Mar 9, 2017Updated 8 years ago
Alternatives and similar repositories for AMBA_AXI3
Users that are interested in AMBA_AXI3 are comparing it to the libraries listed below
Sorting:
- ☆18Apr 5, 2015Updated 10 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 8 months ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- ☆22Feb 22, 2020Updated 5 years ago
- ☆25Feb 26, 2024Updated last year
- uvm AXI BFM(bus functional model)☆265Jun 23, 2013Updated 12 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆12Oct 8, 2017Updated 8 years ago
- Verification IP for APB protocol☆75Dec 18, 2020Updated 5 years ago
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆13Mar 26, 2024Updated last year
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47May 10, 2024Updated last year
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- amba3 apb/axi vip☆53Feb 24, 2015Updated 10 years ago
- Sample UVM code for axi ram dut☆40Dec 14, 2021Updated 4 years ago
- Maven Silicon Project☆20Oct 13, 2018Updated 7 years ago
- VIP for AXI Protocol☆164May 24, 2022Updated 3 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year
- ☆20Nov 18, 2022Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- ☆11May 8, 2022Updated 3 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- ☆13May 5, 2023Updated 2 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago