dpretet / svut

Related projects ⓘ

Alternatives and complementary repositories for svut

• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆146Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated 2 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆76Updated 2 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆114Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆136Updated 2 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆133Updated 5 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆148Updated last week
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆47Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆105Updated 2 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆54Updated 3 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆100Updated last month
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆83Updated 2 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆158Updated 2 years ago
• slaclab / ruckus
  Vivado build system
  ☆71Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆46Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆58Updated last month
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆65Updated 2 weeks ago
• chipsalliance / uvm-verilator
  ☆75Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆85Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆137Updated 3 weeks ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆78Updated 4 months ago