SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
☆79Oct 22, 2024Updated last year
Alternatives and similar repositories for svut
Users that are interested in svut are comparing it to the libraries listed below
Sorting:
- SystemVerilog Logger☆19Sep 30, 2025Updated 5 months ago
- RISCV CPU implementation in SystemVerilog☆32Updated this week
- ☆210Feb 28, 2026Updated 3 weeks ago
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆286Nov 25, 2019Updated 6 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆820Mar 12, 2026Updated last week
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 2 months ago
- Test dashboard for verification features in Verilator☆31Updated this week
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 4 months ago
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆142Feb 18, 2026Updated last month
- The UVM written in Python☆514Updated this week
- Control and status register code generator toolchain☆181Feb 27, 2026Updated 3 weeks ago
- UVM interactive debug library☆35Feb 28, 2026Updated 3 weeks ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆368Updated this week
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated 10 months ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 9 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated last month
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆54Jan 31, 2026Updated last month
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 3 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jan 7, 2026Updated 2 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆66Jan 18, 2025Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Example files for the book FPGA SIMULATION☆23Apr 6, 2017Updated 8 years ago
- ☆28Jan 18, 2021Updated 5 years ago