SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
☆83Oct 22, 2024Updated 2 years ago
Alternatives and similar repositories for svut
Users that are interested in svut are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog Logger☆19Apr 6, 2026Updated 6 months ago
- Test dashboard for verification features in Verilator☆35Oct 24, 2026Updated last week
- RISCV CPU implementation in SystemVerilog☆32Updated this week
- ☆226Aug 16, 2026Updated 2 months ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆292Nov 25, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- ☆13Aug 24, 2026Updated 2 months ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 3 years ago
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- UVM interactive debug library☆36Feb 28, 2026Updated 8 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Python packages providing a library for Verification Stimulus and Coverage☆149Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆209Jun 3, 2026Updated 4 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆854Oct 23, 2026Updated last week
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- AMIQ Externally Controlled Test Bench☆12Jan 13, 2025Updated last year
- Embedded UVM (D Language port of IEEE UVM 1.0)☆35Nov 6, 2025Updated 11 months ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Control and status register code generator toolchain☆227Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- The UVM written in Python☆572Updated this week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- Generate UVM register model from compiled SystemRDL input☆62Nov 25, 2025Updated 11 months ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- Constrained random stimuli generation for C++ and SystemC☆54Nov 29, 2023Updated 2 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆495Oct 17, 2026Updated last week
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- Repurposing existing HDL tools to help writing better code☆227Sep 23, 2026Updated last month
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 10 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆41Aug 26, 2016Updated 10 years ago