Alternatives and similar repositories for svut

Users that are interested in svut are comparing it to the libraries listed below

• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆128Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 3 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated 3 weeks ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆98Updated 3 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 2 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆69Updated this week
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 4 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆72Updated 10 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated last week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆111Updated this week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆116Updated 4 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆59Updated last month
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆39Updated 6 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆48Updated 4 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆93Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆109Updated 2 years ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆78Updated this week
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆100Updated 3 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆167Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago