Alternatives and similar repositories for svut

Users that are interested in svut are comparing it to the libraries listed below

• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated this week
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆101Updated 2 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 2 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 7 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 8 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated 3 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆28Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆46Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆58Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆90Updated last year
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆215Updated last month
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 7 months ago
• antmicro / verilator-verification-features-tests
  ☆27Updated this week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated 3 weeks ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆76Updated last month