Alternatives and similar repositories for LMAC_CORE3:

Users that are interested in LMAC_CORE3 are comparing it to the libraries listed below

• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• antmicro / nvme-verilog-pcie
  ☆56Updated 2 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆33Updated last month
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆44Updated last year
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆85Updated 3 years ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆30Updated 3 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆35Updated 8 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆41Updated last year
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆43Updated 2 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆61Updated last year
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆34Updated 2 years ago
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆19Updated 4 months ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆26Updated 10 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆17Updated 6 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 6 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆104Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆88Updated 5 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆78Updated 5 years ago