lewiz-support / LMAC_CORE3Links
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
☆46Updated 2 years ago
Alternatives and similar repositories for LMAC_CORE3
Users that are interested in LMAC_CORE3 are comparing it to the libraries listed below
Sorting:
- ☆80Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Verilog Ethernet Switch (layer 2)☆50Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- NVMe Controller featuring Hardware Acceleration☆99Updated 4 years ago
- UART -> AXI Bridge☆68Updated 4 years ago
- Ethernet switch implementation written in Verilog☆55Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 4 months ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- 国产VU13P加速卡资料☆80Updated 9 months ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆34Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Ethernet interface modules for Cocotb☆72Updated 3 months ago
- understanding of cocotb (In Chinese Only)☆20Updated 6 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- ☆44Updated 8 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆146Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆62Updated 3 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- ☆70Updated 4 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆38Updated 9 years ago
- ☆16Updated 4 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆76Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago