lewiz-support / LMAC_CORE3Links
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
☆43Updated 2 years ago
Alternatives and similar repositories for LMAC_CORE3
Users that are interested in LMAC_CORE3 are comparing it to the libraries listed below
Sorting:
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆67Updated 2 years ago
- NVMe Controller featuring Hardware Acceleration☆89Updated 4 years ago
- Ethernet switch implementation written in Verilog☆49Updated 2 years ago
- Verilog Ethernet Switch (layer 2)☆44Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- understanding of cocotb (In Chinese Only)☆17Updated last week
- ☆55Updated 2 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- ☆16Updated 3 years ago
- Implementation of the PCIe physical layer☆42Updated last month
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- ☆59Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆65Updated 7 months ago
- PCIE 5.0 Graduation project (Verification Team)☆73Updated last year
- Hardware Assisted IEEE 1588 IP Core☆29Updated 10 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- AHB DMA 32 / 64 bits☆56Updated 10 years ago