Alternatives and similar repositories for LMAC_CORE3

Users that are interested in LMAC_CORE3 are comparing it to the libraries listed below

• antmicro / nvme-verilog-pcie
  ☆64Updated 2 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆43Updated last year
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆47Updated last year
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆63Updated 7 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆40Updated 2 weeks ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆74Updated 10 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆82Updated 5 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆88Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 5 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆29Updated 10 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆64Updated last year
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆37Updated 8 years ago
• opensmartnic / cocotb_primer
  understanding of cocotb （In Chinese Only）
  ☆17Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆54Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆36Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆72Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆93Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆51Updated 2 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆34Updated 4 years ago