andrewcapatina / cadence_power_switchesLinks
cadence flow for genus and innovus with UPF added.
☆14Updated 4 years ago
Alternatives and similar repositories for cadence_power_switches
Users that are interested in cadence_power_switches are comparing it to the libraries listed below
Sorting:
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆21Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆19Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆85Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆221Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- ☆166Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- VIP for AXI Protocol☆153Updated 3 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆109Updated 11 years ago
- Some useful documents of Synopsys☆87Updated 3 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆108Updated 9 months ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆40Updated last year
- This is the main repository for all the examples for the book Practical UVM☆203Updated 4 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆25Updated last month
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- UVM and System Verilog Manuals☆44Updated 6 years ago
- ☆20Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆76Updated 3 years ago
- AXI总线连接器☆104Updated 5 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆155Updated 5 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆156Updated last year
- ☆48Updated 4 years ago
- ☆13Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆128Updated 7 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆34Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated last year
- Source code repo for UVM Tutorial for Candy Lovers☆199Updated 8 years ago