toddmaustin / bringup-benchLinks
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
☆213Updated last week
Alternatives and similar repositories for bringup-bench
Users that are interested in bringup-bench are comparing it to the libraries listed below
Sorting:
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆284Updated 2 weeks ago
- ☆190Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆232Updated 10 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆189Updated 3 weeks ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆159Updated 3 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆180Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated last week
- RISC-V Virtual Prototype☆177Updated 10 months ago
- Open-source RTL logic simulator with CUDA acceleration☆222Updated 2 weeks ago
- Self checking RISC-V directed tests☆113Updated 4 months ago
- Modeling Architectural Platform☆208Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆268Updated 3 weeks ago
- RISC-V Torture Test☆201Updated last year
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆216Updated last week
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated 3 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆287Updated last week
- ☆89Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆163Updated 5 years ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated last year
- ☆108Updated 2 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆103Updated 3 weeks ago
- RISC-V System on Chip Template☆159Updated last month
- ☆296Updated 3 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆91Updated last month
- Communication framework for RTL simulation and emulation.☆301Updated this week
- high-performance RTL simulator☆178Updated last year