Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
☆225Jun 5, 2026Updated 3 weeks ago
Alternatives and similar repositories for bringup-bench
Users that are interested in bringup-bench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 3 months ago
- VIP-Bench benchmarks for evaluating secure computation frameworks (e.g., HE, MPC, SE, etc...)☆13Jun 9, 2023Updated 3 years ago
- ☆33Jan 7, 2025Updated last year
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Mar 30, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Open source ISS and logic RISC-V 32 bit project☆60Jan 20, 2026Updated 5 months ago
- RISCV lock-step checker based on Spike☆14Mar 6, 2026Updated 3 months ago
- list of links to resources related to functional verification☆12Sep 10, 2023Updated 2 years ago
- Universal Memory Interface (UMI)☆160Updated this week
- Learn RISC-V☆22Dec 5, 2024Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆116Jun 18, 2026Updated last week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆556Updated this week
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆32Feb 2, 2026Updated 4 months ago
- Documentation for RISC-V Spike☆105Oct 18, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆191Mar 10, 2024Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆169Feb 2, 2026Updated 5 months ago
- Communication framework for RTL simulation and emulation.☆316Jun 22, 2026Updated last week
- Code generation tool for control and status registers☆464May 30, 2026Updated last month
- RISC-V Directed Test Framework and Compliance Suite, RiESCUE☆67Jun 23, 2026Updated last week
- ☆35Updated this week
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆270Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Example of how to use UVM with Verilator☆45Apr 20, 2026Updated 2 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆346Updated this week
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 8 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆75Feb 12, 2026Updated 4 months ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆28Jan 6, 2026Updated 5 months ago
- [Moved to Codeberg] Another size-optimized RISC-V CPU for your consideration.☆61May 10, 2026Updated last month
- RISCulator is a RISC-V emulator.