toddmaustin / bringup-benchLinks
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
☆218Updated 2 months ago
Alternatives and similar repositories for bringup-bench
Users that are interested in bringup-bench are comparing it to the libraries listed below
Sorting:
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆228Updated 2 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆194Updated this week
- ☆191Updated 2 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆206Updated 3 weeks ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆299Updated 2 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆312Updated 2 weeks ago
- Modeling Architectural Platform☆214Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆134Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆247Updated 3 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 7 months ago
- RISC-V Virtual Prototype☆184Updated last year
- Ariane is a 6-stage RISC-V CPU☆151Updated 6 years ago
- RISC-V Torture Test☆206Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Self checking RISC-V directed tests☆118Updated 7 months ago
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆168Updated 5 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆398Updated 2 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 3 months ago
- ☆301Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆250Updated last year
- RISC-V Verification Interface☆134Updated 3 weeks ago
- RISC-V System on Chip Template☆159Updated 4 months ago