toddmaustin / bringup-benchLinks
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
☆181Updated 2 months ago
Alternatives and similar repositories for bringup-bench
Users that are interested in bringup-bench are comparing it to the libraries listed below
Sorting:
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆154Updated 3 years ago
- ☆181Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆225Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 7 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆278Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- CVA6 SDK containing RISC-V tools and Buildroot☆69Updated 2 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆170Updated 6 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆180Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆262Updated 3 weeks ago
- Modeling Architectural Platform☆194Updated this week
- Open-source RTL logic simulator with CUDA acceleration☆187Updated 3 weeks ago
- Self checking RISC-V directed tests☆110Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆169Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago
- ☆105Updated last month
- The multi-core cluster of a PULP system.☆105Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆271Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- RISC-V Virtual Prototype☆171Updated 7 months ago
- ☆292Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆69Updated last year
- Ariane is a 6-stage RISC-V CPU☆140Updated 5 years ago
- RISC-V Torture Test☆196Updated last year
- ☆86Updated 3 years ago
- SystemC/TLM-2.0 Co-simulation framework☆251Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Chisel RISC-V Vector 1.0 Implementation☆103Updated 2 months ago
- ☆139Updated last year