toddmaustin / bringup-bench
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
☆151Updated 4 months ago
Alternatives and similar repositories for bringup-bench:
Users that are interested in bringup-bench are comparing it to the libraries listed below
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆150Updated 2 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆158Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆101Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆221Updated last year
- ☆170Updated last year
- Modeling Architectural Platform☆181Updated 2 weeks ago
- RISC-V Torture Test☆186Updated 8 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆69Updated last week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆157Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆88Updated last month
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆89Updated this week
- A Fast, Low-Overhead On-chip Network☆185Updated this week
- Self checking RISC-V directed tests☆102Updated last month
- Vector Acceleration IP core for RISC-V*☆172Updated this week
- Instruction Set Generator initially contributed by Futurewei☆274Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- Ariane is a 6-stage RISC-V CPU☆133Updated 5 years ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆267Updated 2 weeks ago
- ☆279Updated 3 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆89Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆140Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆172Updated 8 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆243Updated this week
- RISC-V IOMMU Specification☆110Updated 2 weeks ago
- ☆150Updated last year
- RISC-V Virtual Prototype☆163Updated 3 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆94Updated 3 years ago