Alternatives and similar repositories for LearnRISC-V

Users that are interested in LearnRISC-V are comparing it to the libraries listed below

• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆102Updated last month
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 2 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆84Updated last week
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆72Updated 2 weeks ago
• saursin / riscv-atom
  An open-source 32-bit RISC-V soft-core processor
  ☆35Updated 2 months ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆56Updated 10 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆132Updated 6 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆115Updated this week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆96Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆23Updated last year
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆46Updated this week
• schoeberl / wildcat
  An implementation of RISC-V
  ☆34Updated last month
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆56Updated 8 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated last week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆68Updated last year
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆48Updated 4 years ago
• digital-design-hq / Digital-Resources
  ☆59Updated 3 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆42Updated 4 years ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆63Updated 3 weeks ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆107Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆211Updated last week
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆77Updated 9 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆63Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆61Updated 5 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆77Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆94Updated 3 weeks ago