maswx / vu13pLinks
国产VU13P加速卡资料
☆79Updated 7 months ago
Alternatives and similar repositories for vu13p
Users that are interested in vu13p are comparing it to the libraries listed below
Sorting:
- ☆79Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆124Updated 3 years ago
- NVMe Controller featuring Hardware Acceleration☆94Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆141Updated last year
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆75Updated last year
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆45Updated 2 years ago
- Verilog Ethernet Switch (layer 2)☆49Updated 2 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆96Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆141Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)☆154Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆56Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆75Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆65Updated 5 months ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆138Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Gigabit Ethernet UDP communication driver☆79Updated 6 years ago
- understanding of cocotb (In Chinese Only)☆20Updated 4 months ago
- Verilog digital signal processing components☆157Updated 2 years ago
- ☆31Updated 4 years ago
- PCI express simulation framework for Cocotb☆179Updated last month
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- IEEE P1735 decryptor for VHDL☆36Updated 10 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- Example designs for FPGA Drive FMC☆268Updated 9 months ago