国产VU13P加速卡资料
☆86Mar 17, 2025Updated last year
Alternatives and similar repositories for vu13p
Users that are interested in vu13p are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)☆219Sep 9, 2023Updated 3 years ago
- Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP☆68Nov 12, 2022Updated 3 years ago
- ☆22Nov 7, 2019Updated 6 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Jun 10, 2026Updated 4 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Gowin USB3.0 Device Controller IP☆18Aug 20, 2024Updated 2 years ago
- FPGA-based SATA-DMA Host Controller☆36Nov 20, 2025Updated 11 months ago
- Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)☆55May 10, 2020Updated 6 years ago
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Mar 28, 2020Updated 6 years ago
- 通用IO测试工程,用于捡垃圾测试IO。与BSDL需要对引脚输入不同,该工程只需要确定时钟输入,然后自动向每个IO发送指定字符串,因此只需要将串口接入任意IO查看输出即可☆19Aug 30, 2026Updated 2 months ago
- NVMe Controller featuring Hardware Acceleration☆123Jun 23, 2021Updated 5 years ago
- Open source FPGA-based NIC and platform for in-network compute☆2,506Jul 5, 2024Updated 2 years ago
- Plug & Play.☆59Updated this week
- ☆91Jun 27, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆869Sep 14, 2023Updated 3 years ago
- AMD OpenNIC Project Overview☆348Dec 20, 2022Updated 3 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆33Jul 7, 2026Updated 3 months ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆180Mar 20, 2025Updated last year
- ☆20Sep 15, 2021Updated 5 years ago
- ☆39Mar 10, 2021Updated 5 years ago
- A module for TBT3☆48May 11, 2026Updated 5 months ago
- Small footprint and configurable PCIe core☆740Updated this week
- 使用Cordic算法函数运算,在资源受限的设备上运行(如资源较少的FPGA、嵌入式MCU),避免了浮点运算、乘法、除法,只用移位和加法函数的计算。☆14Mar 22, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AMD OpenNIC driver includes the Linux kernel driver☆86Jan 3, 2025Updated last year
- ☆26Oct 8, 2019Updated 7 years ago
- Alibaba Cloud AS02MC04 hack☆82Jul 17, 2026Updated 3 months ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 12 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆112Oct 3, 2019Updated 7 years ago
- Example designs for FPGA Drive FMC☆305Oct 26, 2026Updated last week
- ☆42Jun 9, 2022Updated 4 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆977Oct 21, 2026Updated last week
- The official repository of the local FPGA Development Kit.☆22Apr 30, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other t…☆391Updated this week
- Blockchain Offload Engine☆17May 5, 2018Updated 8 years ago
- FPGA board-level debugging and reverse-engineering tool☆46Mar 24, 2023Updated 3 years ago
- This repo contains the Limago code☆99May 8, 2025Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- USB3 SuperSpeed (5Gbps) and SuperSpeedPlus (10Gbps) for FPGAs without external chip: PHY + Device Core in LiteX.☆274Updated this week
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆292Jun 4, 2026Updated 4 months ago