FernandoGuiomar / CPR_VHDL
VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems
☆13Updated 4 years ago
Alternatives and similar repositories for CPR_VHDL:
Users that are interested in CPR_VHDL are comparing it to the libraries listed below
- Playground for implementing LDPC codes on FPGA☆15Updated 2 years ago
- Repository containing the DSP gateware cores☆12Updated 5 months ago
- A project demonstrate how to config ad9361 to TX mode☆11Updated 6 years ago
- IEEE 802.16 OFDM-based transceiver system☆23Updated 5 years ago
- FPGA firmware for FPGA radio baseband board. Scroll down for README.☆16Updated 5 years ago
- Miniature 8GHz FMCW Radar☆11Updated 8 years ago
- 4-Layer XC7Z010 DDR3 Layout☆15Updated 3 years ago
- Radio Spectrum Viewer and Software Defined Radio in a cheap FPGA board☆11Updated last year
- Partial Verilog implimentation of a WiMAX OFDM Phy☆18Updated 12 years ago
- Verilog modules for software-defined radio.☆18Updated 12 years ago
- The implementation of AD9371 on KC705☆20Updated 4 years ago
- RF Signal Generator with filtered outputs, modulation features☆13Updated 4 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆11Updated 4 years ago
- The source codes of the fast x86 LDPC decoder published☆25Updated 4 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆26Updated 3 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆17Updated 8 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆13Updated 4 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆26Updated 4 months ago
- USB-PD-3.1-Verilog☆12Updated 10 months ago
- My code repositry for common use.☆22Updated 3 years ago
- FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method☆10Updated 8 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Updated last month
- Verilog IP Cores & Tests☆13Updated 6 years ago
- ☆13Updated 4 years ago
- easy to use RX and TX handler for the Adalm - Pluto☆14Updated 2 years ago
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago
- SpaceVNX (VITA 74.4) carrier based on Zynq-7000.☆12Updated 2 years ago
- Yet Another XC7Z010 Board☆17Updated 2 years ago
- A USRP B200 compatible GPSDO board with the u-blox LEA-M8F☆13Updated 8 years ago
- The FPGA design for the FreeSRP's Artix 7 FPGA☆24Updated 7 years ago