Lombiq / Hastlayer-Hardware-Framework---Catapult
Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.
☆12Updated 5 years ago
Alternatives and similar repositories for Hastlayer-Hardware-Framework---Catapult
Users that are interested in Hastlayer-Hardware-Framework---Catapult are comparing it to the libraries listed below
Sorting:
- Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)☆41Updated 5 years ago
- ☆18Updated 3 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 5 years ago
- ☆46Updated 3 years ago
- Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP☆55Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆17Updated 9 months ago
- Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)☆22Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- ☆20Updated 5 years ago
- Mirror of NeTV FPGA Verilog Code☆13Updated 13 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- ☆17Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Updated 3 years ago
- Extensible FPGA control platform☆60Updated 2 years ago
- Control a MIPI Camera over I2C☆21Updated 4 years ago
- USB 1.1 Host and Function IP core☆22Updated 10 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- Open FPGA Modules☆23Updated 7 months ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Updated 7 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- ☆14Updated last year
- ULPI Link Wrapper (USB Phy Interface)☆26Updated 5 years ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- FPGA board-level debugging and reverse-engineering tool☆37Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Wishbone to AXI bridge (VHDL)☆41Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- USB -> AXI Debug Bridge☆38Updated 3 years ago