Alternatives and similar repositories for storey-peak:

Users that are interested in storey-peak are comparing it to the libraries listed below

• j-marjanovic / pp-sp-reference-design
  ☆44Updated 3 years ago
• j-marjanovic / jtag-quartus-ft232h
  ☆45Updated 3 years ago
• tow3rs / jtag-mpsse-blaster
  Use an MPSSE FTDI device as a JTAG interface in Quartus tools
  ☆20Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• wirebond / catapult_v2_pikes_peak
  Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)
  ☆41Updated 4 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• racerxdl / pcieledblink
  Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)
  ☆22Updated 3 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆36Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated 11 months ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆42Updated 4 years ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆28Updated 4 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆56Updated 4 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated 10 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• kholia / xvcpi
  Use Raspberry Pi as a wireless Xilinx JTAG 'cable'. Note: This is a portable, tested, maintained clone of https://github.com/strongleg/xv…
  ☆35Updated 3 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆51Updated last year
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆61Updated 3 weeks ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆31Updated 9 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 2 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 2 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆53Updated 2 years ago
• j-marjanovic / otma-pin-re
  ☆17Updated 3 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• freecores / uart16550
  UART 16550 core
  ☆33Updated 10 years ago
• j-marjanovic / pp-sp-linux-driver
  ☆12Updated 3 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆35Updated 6 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆85Updated 6 years ago