Alternatives and similar repositories for pp-sp-reference-design

Users that are interested in pp-sp-reference-design are comparing it to the libraries listed below

• j-marjanovic / jtag-quartus-ft232h
  ☆53Updated 3 years ago
• j-marjanovic / otma-pin-re
  ☆18Updated 4 years ago
• carlosedp / chisel-fpga-pinfinder
  A Chisel implementation for an FPGA Pin Finder thru UART
  ☆17Updated last year
• tow3rs / catapult-v3-smartnic-re
  Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
  ☆155Updated 2 years ago
• j-marjanovic / pp-sp-linux-driver
  ☆14Updated 4 years ago
• ruurdk / storey-peak
  Collected resources and getting started with Azure PCIe FPGA device
  ☆32Updated 8 months ago
• wirebond / catapult_v2_pikes_peak
  Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)
  ☆44Updated 5 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆82Updated 2 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆96Updated 5 years ago
• merlinepedra25 / Xilinx-Unprotect
  ☆53Updated 3 years ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆51Updated 5 months ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆82Updated last year
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆100Updated 6 years ago
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆236Updated 3 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆102Updated 2 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆41Updated 5 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆185Updated last year
• TiferKing / ypcb_00338_1p1_hack
  YPCB-00338-1P1 Hack
  ☆72Updated 10 months ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆95Updated 5 years ago
• enjoy-digital / litesata
  Small footprint and configurable SATA core
  ☆153Updated last month
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆57Updated 2 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆58Updated 4 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆38Updated 10 years ago
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆48Updated 2 years ago
• mmicko / prjtang
  Documenting the Anlogic FPGA bit-stream format.
  ☆88Updated 2 years ago