Alternatives and similar repositories for catapult-v3-smartnic-re

Users that are interested in catapult-v3-smartnic-re are comparing it to the libraries listed below

• maswx / vu13p
  国产VU13P加速卡资料
  ☆76Updated 4 months ago
• thinkoco / microsoft_fpga
  Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP
  ☆57Updated 2 years ago
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆71Updated last month
• wirebond / catapult_v2_pikes_peak
  Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)
  ☆41Updated 5 years ago
• sipeed / TangMega-138KPro-example
  Tang Mega 138K Pro examples
  ☆75Updated 3 months ago
• TiferKing / ypcb_00338_1p1_hack
  YPCB-00338-1P1 Hack
  ☆57Updated 7 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆122Updated 2 months ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆73Updated last year
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆122Updated 2 years ago
• j-marjanovic / pp-sp-reference-design
  ☆46Updated 3 years ago
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆221Updated 3 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆235Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆80Updated last year
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆35Updated 10 years ago
• antmicro / nvme-verilog-pcie
  ☆73Updated 3 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆125Updated 2 years ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆306Updated 3 months ago
• j-marjanovic / jtag-quartus-ft232h
  ☆47Updated 3 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆250Updated 2 weeks ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆90Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆66Updated 8 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• CospanDesign / nysa-sata
  ☆86Updated 8 years ago
• risclite / R8051
  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
  ☆187Updated 5 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆63Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆146Updated 2 years ago