tow3rs / catapult-v3-smartnic-reView external linksLinks
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
☆165Sep 9, 2023Updated 2 years ago
Alternatives and similar repositories for catapult-v3-smartnic-re
Users that are interested in catapult-v3-smartnic-re are comparing it to the libraries listed below
Sorting:
- Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP☆65Nov 12, 2022Updated 3 years ago
- Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)☆48May 10, 2020Updated 5 years ago
- ☆18May 24, 2021Updated 4 years ago
- ☆51Oct 30, 2021Updated 4 years ago
- ☆55Mar 27, 2022Updated 3 years ago
- Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)☆23Aug 2, 2021Updated 4 years ago
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Mar 28, 2020Updated 5 years ago
- 国产VU13P加速卡资料☆83Mar 17, 2025Updated 11 months ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆25May 31, 2020Updated 5 years ago
- A module for TBT3☆44Dec 31, 2023Updated 2 years ago
- ☆15Oct 30, 2021Updated 4 years ago
- Plug & Play.☆47Nov 29, 2025Updated 2 months ago
- A Chisel implementation for an FPGA Pin Finder thru UART☆17Sep 24, 2024Updated last year
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆29Feb 22, 2024Updated last year
- Simple framework for building PCIe-based solutions for Altera FPGAs☆53Mar 18, 2020Updated 5 years ago
- Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development☆75May 19, 2025Updated 8 months ago
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆17May 20, 2022Updated 3 years ago
- Collected resources and getting started with Azure PCIe FPGA device☆38Feb 24, 2025Updated 11 months ago
- Alibaba Cloud AS02MC04 hack☆37Jan 7, 2025Updated last year
- FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)☆23Jan 15, 2022Updated 4 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- ☆38Jan 7, 2022Updated 4 years ago
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- BaseBoard design for QMTech Kintex 7 FPGA☆22Aug 24, 2022Updated 3 years ago
- FPGA board-level debugging and reverse-engineering tool☆39Mar 24, 2023Updated 2 years ago
- Xilinx Virtual Cable implementation for ESP32☆38Jul 23, 2021Updated 4 years ago
- ☆14Aug 1, 2023Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆2,206Jul 5, 2024Updated last year
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 2 years ago
- USB3 PIPE interface for Xilinx 7-Series☆246Jan 2, 2026Updated last month
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- LZW Compressoion algorithm in verilog☆17Dec 19, 2013Updated 12 years ago
- ☆95Sep 29, 2025Updated 4 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Feb 4, 2024Updated 2 years ago
- NVMe Controller featuring Hardware Acceleration☆101Jun 23, 2021Updated 4 years ago
- The 'missing header' for Chisel☆23Feb 5, 2026Updated last week
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- RISC CPU by Icenowy☆12Dec 26, 2018Updated 7 years ago