Alternatives and similar repositories for catapult_v2_pikes_peak

Users that are interested in catapult_v2_pikes_peak are comparing it to the libraries listed below

• j-marjanovic / jtag-quartus-ft232h
  ☆46Updated 3 years ago
• thinkoco / microsoft_fpga
  Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP
  ☆55Updated 2 years ago
• j-marjanovic / otma-pin-re
  ☆18Updated 4 years ago
• j-marjanovic / pp-sp-reference-design
  ☆46Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆90Updated 4 years ago
• j-marjanovic / ocs-tray-mezzanine-adapter
  PCIe adapter for an FPGA accelerator for Open CloudServer
  ☆23Updated 5 years ago
• Lombiq / Hastlayer-Hardware-Framework---Catapult
  Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.
  ☆12Updated 5 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 4 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆39Updated 5 years ago
• TiferKing / ypcb_00338_1p1_hack
  YPCB-00338-1P1 Hack
  ☆47Updated 5 months ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆43Updated 3 years ago
• ruurdk / storey-peak
  Collected resources and getting started with Azure PCIe FPGA device
  ☆20Updated 3 months ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆38Updated 4 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆44Updated 5 years ago
• tow3rs / jtag-mpsse-blaster
  Use an MPSSE FTDI device as a JTAG interface in Quartus tools
  ☆21Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated last week
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆78Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• racerxdl / pcieledblink
  Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)
  ☆23Updated 3 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆65Updated 3 weeks ago