Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
☆26Feb 21, 2022Updated 4 years ago
Alternatives and similar repositories for vexriscv_ocd_blog
Users that are interested in vexriscv_ocd_blog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆18Nov 16, 2023Updated 2 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆15Jan 19, 2024Updated 2 years ago
- VexRiscV system with GDB-Server in Hardware☆21Jul 5, 2023Updated 2 years ago
- ☆10Jun 9, 2022Updated 3 years ago
- Simple UVM environment for experimenting with Verilator.☆38Mar 23, 2026Updated 3 weeks ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- Next186 SoC PC☆17Feb 5, 2014Updated 12 years ago
- A collection of little open source FPGA hobby projects☆51Feb 6, 2020Updated 6 years ago
- This repository contains sample code integrating Renode with Verilator☆26May 27, 2025Updated 10 months ago
- RISCV CPU implementation in SystemVerilog☆32Mar 17, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)☆23Jan 15, 2022Updated 4 years ago
- A 5$ Xilinx ZYNQ development board.☆28Jan 25, 2023Updated 3 years ago
- 移植LWIP，支持freeRTOS和socket编程☆10Mar 8, 2019Updated 7 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- Mini CPU design with JTAG UART support☆21Jun 8, 2021Updated 4 years ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 8 years ago
- Picorv32 SoC on the TinyFPGA BX, for games etc.☆12Sep 22, 2018Updated 7 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated last year
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- IP submodules, formatted for easier CI integration☆31Sep 22, 2025Updated 6 months ago
- lwip with simple IPsec and MACsec implementations☆12Jun 24, 2022Updated 3 years ago
- ADPCM decoder compatible with OKI 6295☆15Jan 6, 2025Updated last year
- the engine of guardians☆13May 28, 2013Updated 12 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆13Nov 26, 2024Updated last year
- ☆11Jan 9, 2021Updated 5 years ago
- Docker RISC-V 64 GCC and Spike RISC-V ISA Simulator☆12Jan 30, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Mega/Xmega soft core RTL design.☆11Feb 21, 2020Updated 6 years ago
- Code to support porting MiST cores to other boards.☆48Feb 26, 2026Updated last month
- ☆10Nov 8, 2019Updated 6 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆54Feb 2, 2026Updated 2 months ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆12Sep 22, 2020Updated 5 years ago
- The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.☆14Jan 27, 2016Updated 10 years ago
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆18Dec 23, 2020Updated 5 years ago