Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
☆26Feb 21, 2022Updated 4 years ago
Alternatives and similar repositories for vexriscv_ocd_blog
Users that are interested in vexriscv_ocd_blog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- ☆19Aug 27, 2022Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆15Jan 19, 2024Updated 2 years ago
- VexRiscV system with GDB-Server in Hardware☆21Jul 5, 2023Updated 3 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 4 months ago
- A collection of little open source FPGA hobby projects☆51Feb 6, 2020Updated 6 years ago
- ☆41Jan 23, 2024Updated 2 years ago
- A 5$ Xilinx ZYNQ development board.☆28Jan 25, 2023Updated 3 years ago
- FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)☆25Jan 15, 2022Updated 4 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- 移植LWIP,支持freeRTOS和socket编程☆10Mar 8, 2019Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- Simple UVM environment for experimenting with Verilator.☆44Aug 1, 2026Updated 3 weeks ago
- Mega/Xmega soft core RTL design.☆11Feb 21, 2020Updated 6 years ago
- WAyereless Site SUrveying Program☆12Feb 9, 2016Updated 10 years ago
- scala template engine and simple expression evaluator☆11Feb 11, 2024Updated 2 years ago
- FPGA core for ISO7816 smart card communication☆14Apr 28, 2022Updated 4 years ago
- PaserTech PaskiSoC 一个低成本的riscv soc实现, 支 持32bit linux with mmu☆20May 27, 2025Updated last year
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆12Sep 22, 2020Updated 5 years ago
- Picorv32 SoC on the TinyFPGA BX, for games etc.☆12Sep 22, 2018Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆15Feb 21, 2023Updated 3 years ago
- ☆16Jan 12, 2021Updated 5 years ago
- 在沁恒的CH554 T&E&G MINIEVT2开发板上实现USB键盘和鼠标符合设备。☆23Sep 23, 2022Updated 3 years ago
- IP submodules, formatted for easier CI integration☆31Sep 22, 2025Updated 11 months ago
- A simple 6502 system built on a Lattice Ultra Plus 5k FPGA☆15Mar 11, 2019Updated 7 years ago
- Tools for analyzing and browsing Tarmac instruction traces.☆86Jun 5, 2026Updated 2 months ago
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated last year
- lwip with simple IPsec and MACsec implementations☆12Jun 24, 2022Updated 4 years ago
- ☆15Dec 9, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆11Jan 9, 2021Updated 5 years ago
- The biologically plausible self backpropagation on SNNs and ANNs☆13Aug 27, 2021Updated 5 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆14Nov 26, 2024Updated last year
- A wrapper around Minecraft Raspberry Pi to get it working on Novena☆11Sep 25, 2013Updated 12 years ago
- Code to support porting MiST cores to other boards.☆49Feb 26, 2026Updated 6 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆56Feb 2, 2026Updated 6 months ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆10Sep 17, 2019Updated 6 years ago