Alternatives and similar repositories for Accellant

Users that are interested in Accellant are comparing it to the libraries listed below

• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆48Updated 2 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆17Updated 4 years ago
• merledu / symbiflow-magic
  This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
  ☆10Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆42Updated 2 months ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆59Updated 3 years ago
• sam210723 / fpga
  Collection of projects for various FPGA development boards
  ☆44Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆57Updated 2 weeks ago
• fontamsoc / pu32
  ☆15Updated last year
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆29Updated 3 years ago
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆147Updated 3 years ago
• DoctorWkt / ULX3S-Blinky
  A blinky project for the ULX3S v3.0.3 FPGA board
  ☆16Updated 6 years ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆56Updated last year
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 8 months ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 4 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆32Updated 8 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆39Updated 2 weeks ago
• mattvenn / crap-o-scope
  crap-o-scope scope implementation for icestick
  ☆20Updated 6 years ago
• mattvenn / fpga-sram
  mystorm sram test
  ☆27Updated 7 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆91Updated 8 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 2 years ago
• whitequark / bfcpu2
  A pipelined brainfuck softcore in Verilog
  ☆19Updated 10 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• Mr-Bossman / KISC-V
  KISCV, a KISS principle riscv32i CPU
  ☆21Updated 4 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• ultraembedded / riscv32_linux_from_scratch
  RISC-V 32-bit Linux From Scratch
  ☆32Updated 5 years ago