SocKit 1-wire (onewire) master
☆19Aug 5, 2012Updated 13 years ago
Alternatives and similar repositories for sockit_owm
Users that are interested in sockit_owm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- A set of small Verilog projects, to simulate and implement on FPGA development boards☆15Mar 5, 2018Updated 8 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Feb 25, 2026Updated last month
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 7 months ago
- Blinking Led Project☆10Aug 29, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)☆15Jan 5, 2026Updated 2 months ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- ☆13Jul 27, 2025Updated 8 months ago
- Python classes to create agnostic wave files for HDL simulator viewer☆12Mar 8, 2020Updated 6 years ago
- Experiments with Marsohod3GW board with Gowin FPGA chip☆17May 8, 2025Updated 10 months ago
- Fullsearch based Motion Estimation Processor written in Verilog-HDL☆11Feb 19, 2017Updated 9 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆23Feb 20, 2017Updated 9 years ago
- a USB2 highspeed device core, written in amaranth HDL☆53Sep 17, 2024Updated last year
- Gestion de piscine via arduino☆19May 6, 2017Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Acceleration for an s-curve shaped speed☆12Jun 19, 2024Updated last year
- Master-thesis-final☆19Oct 9, 2023Updated 2 years ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Mar 15, 2026Updated last week
- Multi-Technology RAM with AHB3Lite interface☆25May 10, 2024Updated last year
- cocotb code library☆13Dec 28, 2020Updated 5 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Jan 10, 2018Updated 8 years ago
- Homebrew tap for ceph-fuse on catalina with nautilus supported☆11Jul 6, 2020Updated 5 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆26Dec 5, 2024Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Gate array reverse engineering☆29Dec 28, 2025Updated 2 months ago
- Public resources available for Xilinx MPSOC+ and SDSOC hardware☆18May 26, 2017Updated 8 years ago
- ☆14Oct 6, 2023Updated 2 years ago
- A small bash utility to show lvmcache statistics☆12Dec 28, 2016Updated 9 years ago
- Port knocking daemon with web interface☆14Jan 3, 2018Updated 8 years ago
- Legacy Source Code for Dragino Yun firmware with ver 1.3.x☆16Jan 16, 2015Updated 11 years ago
- ☆14Mar 9, 2026Updated 2 weeks ago
- Diablo build for BigEndian and SDL1.2 systems☆10Sep 15, 2020Updated 5 years ago
- FPGA implementation of a CDR targeting a Xilinx Kintex-7 for data rates up to 250 MHz☆19Nov 15, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Rust binding for the Rime Input Method Engine.☆16Jan 8, 2019Updated 7 years ago
- All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)☆31Jan 25, 2016Updated 10 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- SEGA Genesis/Megadrive FPGA core☆13Nov 28, 2018Updated 7 years ago
- A python client for the Beckhoff Twincat AMS/ADS protocoll☆20Mar 4, 2015Updated 11 years ago
- 96Boards camera support from Deltavison :☆42Apr 28, 2018Updated 7 years ago
- MiniMig for TurboChameleon64☆19Nov 16, 2019Updated 6 years ago