jeras / sockit_owm
SocKit 1-wire (onewire) master
☆18Updated 12 years ago
Related projects: ⓘ
- Freecores website☆19Updated 7 years ago
- USB Full Speed PHY☆38Updated 4 years ago
- Wishbone controlled I2C controllers☆40Updated 6 months ago
- WISHBONE Builder☆13Updated 8 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆32Updated 5 years ago
- ☆20Updated this week
- turbo 8051☆28Updated 7 years ago
- Connecting FPGA and MCU using Ethernet RMII☆22Updated 8 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆21Updated 3 years ago
- Wishbone interconnect utilities☆34Updated 3 months ago
- Small footprint and configurable JESD204B core☆39Updated 3 months ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 8 years ago
- AVR Core☆12Updated 10 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆49Updated last year
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆31Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆31Updated 4 years ago
- Yet another free 8051 FPGA core☆28Updated 6 years ago
- Verilog Repository for GIT☆28Updated 3 years ago
- ☆18Updated 4 years ago
- VHDL Modules☆23Updated 9 years ago
- Extensible FPGA control platform☆52Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆32Updated 5 years ago
- Universal Advanced JTAG Debug Interface☆17Updated 4 months ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆27Updated 6 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆42Updated 8 years ago
- usb-jtag - Altera USB Blaster Emulation with a FX2☆69Updated 3 years ago
- Small footprint and configurable SPI core☆38Updated this week
- CMod-S6 SoC☆35Updated 6 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago