Daniel-And-Jorge / 6.111-Final-Project
☆11Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for 6.111-Final-Project
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆55Updated 2 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆28Updated 3 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated last year
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆106Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆40Updated 7 months ago
- ☆16Updated 4 months ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆54Updated 3 years ago
- ☆29Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 5 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆41Updated 3 years ago
- Master-thesis-final☆18Updated last year
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-s…☆18Updated 6 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆77Updated last year
- assorted library of utility cores for amaranth HDL☆81Updated 2 months ago
- Projects published on controlpaths.com and hackster.io☆40Updated 2 years ago
- Various JTAG boundary scan tools☆33Updated 3 years ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆26Updated 5 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆24Updated 5 months ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆12Updated 7 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆34Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated 2 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆22Updated 4 months ago
- An 8b10b decoder and encoder in logic in VHDL☆16Updated 3 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆60Updated last month
- Tester for IS61WV5128BLL-10BLI SRAM in Cmod A7-35T☆18Updated 6 years ago