A tiny Python package to parse spice raw data files.
☆53Dec 26, 2022Updated 3 years ago
Alternatives and similar repositories for spyci
Users that are interested in spyci are comparing it to the libraries listed below
Sorting:
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆55Jun 30, 2017Updated 8 years ago
- Generate SVG schematics and block diagrams without a mouse.☆31Jul 5, 2025Updated 8 months ago
- A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep☆14Oct 20, 2022Updated 3 years ago
- A python3 gm/ID starter kit☆66Jan 26, 2026Updated last month
- repository for a bandgap voltage reference in SKY130 technology☆42Jan 20, 2023Updated 3 years ago
- Circuit Automatic Characterization Engine☆53Feb 7, 2025Updated last year
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Feb 15, 2024Updated 2 years ago
- Hardware Description Library☆88Feb 17, 2026Updated 2 weeks ago
- ☆340Jan 13, 2026Updated last month
- Hdl21 Schematics☆16Jan 24, 2024Updated 2 years ago
- Python interface for Cadence Spectre☆23Feb 17, 2026Updated 2 weeks ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆72Updated this week
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆34Jun 22, 2025Updated 8 months ago
- Interchange formats for chip design.☆37Feb 15, 2026Updated 3 weeks ago
- Simple and most probably incomplete parser for spectre netlists☆14Oct 4, 2016Updated 9 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆17Mar 28, 2025Updated 11 months ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆444Feb 28, 2026Updated last week
- XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.☆181Nov 17, 2025Updated 3 months ago
- An innovative Verilog-A compiler - reloaded☆39Feb 26, 2026Updated last week
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated 2 months ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 2 years ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆118Nov 21, 2025Updated 3 months ago
- Read Spectre PSF files☆73Dec 12, 2025Updated 2 months ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆55Feb 14, 2026Updated 3 weeks ago
- Simulate electronic circuit using Python and the Ngspice / Xyce simulators☆793Aug 13, 2024Updated last year
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆90Dec 18, 2024Updated last year
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Apr 19, 2022Updated 3 years ago
- A stochastic circuit optimizer for Cadence Virtuoso, using the NSGA-II genetic algorithm.☆12Dec 12, 2021Updated 4 years ago
- An Open-Source ASIC Design Template for the SG13G2 IHP Open-PDK.☆17Feb 20, 2026Updated 2 weeks ago
- This repository is for (pre-)release versions of the Revolution EDA.☆60Feb 24, 2026Updated last week
- PLL Designs on Skywater 130nm MPW☆24Dec 3, 2023Updated 2 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆208Feb 26, 2026Updated last week
- Python bindings for ngspice simulation engine☆73Mar 11, 2020Updated 5 years ago
- Jupyter kernel for Cadence SKILL☆22Feb 16, 2017Updated 9 years ago
- This library is an attempt to make transistor sizing for Analog design less painful.☆22Jan 22, 2026Updated last month
- A Python and SKILL Framework for Cadence Virtuoso☆49Dec 13, 2025Updated 2 months ago
- LAYout with Gridded Objects v2☆67Jun 22, 2025Updated 8 months ago
- EM simulation scripts to simulate passive devices on Skywater 130nm open-source process. (Octave interface only for now)☆13Jan 7, 2024Updated 2 years ago
- Custom IC Design Platform☆46Updated this week