Alternatives and similar repositories for core-v-sdk

Users that are interested in core-v-sdk are comparing it to the libraries listed below

• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆101Updated 7 months ago
• pulp-platform / pulp-sdk
  ☆123Updated 2 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆130Updated 3 years ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆179Updated last week
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆192Updated 2 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆129Updated 6 years ago
• lowRISC / lowrisc-toolchains
  UNSUPPORTED INTERNAL toolchain builds
  ☆47Updated last week
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆101Updated 5 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆129Updated last week
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆84Updated 3 weeks ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆159Updated 8 months ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆164Updated 2 years ago
• edaplayground / eda-playground
  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
  ☆67Updated last week
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆153Updated 4 months ago
• chipsalliance / VeeR-ISS
  ☆151Updated 2 years ago
• pulp-platform / ri5cy_gnu_toolchain
  ☆23Updated 10 months ago
• The-OpenROAD-Project / megaboom
  ☆33Updated last week
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆73Updated 3 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated last week
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆239Updated this week
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆133Updated 5 years ago
• parasjaing7 / avsdpll_3v3
  This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…
  ☆15Updated 4 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆47Updated 3 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆196Updated 2 months ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆80Updated 2 years ago
• chipsalliance / uvm-verilator
  ☆114Updated 3 months ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆94Updated last year
• Xilinx / Embedded-Design-Tutorials
  ☆158Updated last month
• google / open-source-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google.
  ☆109Updated 3 years ago