This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/) workshop.
☆17Jan 30, 2023Updated 3 years ago
Alternatives and similar repositories for Physical-Design-With-OpenLANE-and-SKY130
Users that are interested in Physical-Design-With-OpenLANE-and-SKY130 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆14Dec 29, 2022Updated 3 years ago
- ☆16Apr 8, 2023Updated 3 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- zero-riscy CPU Core☆19Jun 10, 2018Updated 8 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- simple hyperram controller☆12Feb 10, 2019Updated 7 years ago
- This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks re…☆15Sep 7, 2025Updated 9 months ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 2 months ago
- ☆10Nov 30, 2022Updated 3 years ago
- This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains ever…☆41Jul 29, 2024Updated last year
- Learn RISC-V☆22Dec 5, 2024Updated last year
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆84Sep 17, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated last year
- ☆21Nov 22, 2021Updated 4 years ago
- ☆25Dec 31, 2024Updated last year
- ☆17Jan 13, 2024Updated 2 years ago
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 7 years ago
- Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah☆17Oct 19, 2024Updated last year
- mojito☆12May 1, 2018Updated 8 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- VS Code extension for EDAcation - Learning environment for digital hardware design.☆18Jun 3, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆25Mar 7, 2019Updated 7 years ago
- Organic Electronic Device Simulator☆16Dec 14, 2019Updated 6 years ago
- a simple riscv cpu☆24Dec 2, 2022Updated 3 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆29Feb 21, 2019Updated 7 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated last month
- ☆27May 9, 2025Updated last year
- krew-wasm offers a way to write and distribute kubectl plugins based on WebAssembly☆14Apr 15, 2024Updated 2 years ago
- ☆13Aug 29, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Parallel implementation of Smith–Waterman using OpenMP☆10Oct 28, 2020Updated 5 years ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated last year
- ☆43May 26, 2018Updated 8 years ago
- SystemVerilog file list pruner☆19Mar 2, 2026Updated 3 months ago
- ☆26Feb 22, 2024Updated 2 years ago
- deltaV is a bare-metal hypervisor. (Raspberry Pi-3B) [ARMv8-A]☆13May 12, 2024Updated 2 years ago
- Small KVM-based hypervisor, boots Linux (WIP)☆14May 5, 2024Updated 2 years ago