Alternatives and similar repositories for ipcp-dsp:

Users that are interested in ipcp-dsp are comparing it to the libraries listed below

• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆13Updated 3 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆29Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆35Updated 2 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆16Updated 4 years ago
• gem5-hpca-2023 / gem5-tutorial-codespace
  ☆20Updated last year
• hanhwi / SimPoint
  ☆12Updated 2 years ago
• zeal4u / PMP
  About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.
  ☆14Updated 2 years ago
• car3s / IPCP_ISCA2020
  Source codes for "Bouquet of Instruction Pointers"
  ☆16Updated 4 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 7 months ago
• Quangmire / ChampSim
  ChampSim repository
  ☆29Updated last month
• cry-daniel / Computer-Architecture-Learning
  ☆60Updated 2 years ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆23Updated last year
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆25Updated 2 weeks ago
• miaochenlu / Gem5_tutorials
  ☆19Updated last year
• yousei-github / ChampSim-Ramulator
  A simulator integrates ChampSim and Ramulator.
  ☆15Updated 11 months ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• pku-liang / ksim
  ☆40Updated 3 months ago
• SamAinsworth / gem5-triangel
  ☆13Updated last month
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆13Updated 9 months ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆24Updated last month
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• OpenXiangShan / GEM5
  ☆80Updated this week
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 2 months ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated 3 months ago
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆24Updated 3 weeks ago
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆33Updated 6 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆61Updated last year