Alternatives and similar repositories for Red_Tracker

Users that are interested in Red_Tracker are comparing it to the libraries listed below

• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆32Updated 6 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆29Updated 7 months ago
• grant4001 / MNIST_Classification_FPGA
  ☆26Updated 5 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• zhujingyang520 / vlsi_project
  The template for VLSI project
  ☆22Updated 6 years ago
• Marco-Winzker / FPGA-Vision
  Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …
  ☆42Updated last year
• vsdip / avsddac_3v3_sky130_v2
  ☆17Updated 3 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• zhangmozhe / microshift_compression
  Microshift Compression: An Efficient Image Compression Algorithm for Hardware
  ☆32Updated 4 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆32Updated 2 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• wmy367 / Radix-2-division
  unsigned Radix-2 SRT division,基2除法
  ☆15Updated 10 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 7 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆65Updated 5 months ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆24Updated 6 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆21Updated 3 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆15Updated 2 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 9 months ago
• lllibano / LABFT
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…
  ☆14Updated 2 months ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆15Updated 6 years ago
• amiq-consulting / image-upscaling-CNN
  How to Accelerate an Image Upscaling CNN on FPGA Using HLS
  ☆25Updated 4 years ago
• ucb-art / fft
  ☆20Updated 5 years ago
• mbits-mirafra / i3c_avip
  Verification IP project for I3C protocol
  ☆20Updated 7 months ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆50Updated 4 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 5 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated last week
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆51Updated 2 years ago