jevinskie / aes-over-pcie
A VHDL implementation of 128 bit AES encryption with a PCIe interface.
☆26Updated 8 years ago
Alternatives and similar repositories for aes-over-pcie:
Users that are interested in aes-over-pcie are comparing it to the libraries listed below
- A padring generator for ASICs☆25Updated last year
- SoftCPU/SoC engine-V☆54Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Generic Logic Interfacing Project☆44Updated 4 years ago
- Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr☆26Updated 4 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated this week
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- PicoRV☆44Updated 5 years ago
- Virtual development board for HDL design☆40Updated last year
- Wishbone interconnect utilities☆38Updated last week
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- ☆20Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated last week
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆25Updated 6 years ago
- Extensible FPGA control platform☆57Updated last year
- Generate symbols from HDL components/modules☆20Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆14Updated 2 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆26Updated 2 years ago
- Library of reusable VHDL components☆27Updated 11 months ago
- sample VCD files☆36Updated last year
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago