JeremyV2014 / VerilogSHA256Miner

Related projects ⓘ

Alternatives and complementary repositories for VerilogSHA256Miner

• Goshik92 / SHA256Hasher
  SHA-256 IP core for ZedBoard (Zynq SoC)
  ☆29Updated 6 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• rnz / verilog-sha256
  Implementation of the SHA256 Algorithm in Verilog
  ☆37Updated 12 years ago
• wisp / rfid-verilog
  RFID tag and tester in Verilog
  ☆36Updated 11 years ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆25Updated 4 years ago
• unixb0y / SystemVerilogSHA256
  SHA256 in (System-) Verilog / Open Source FPGA Miner
  ☆75Updated 6 years ago
• akhan3 / async-fifo
  Asynchronous FIFO for transferring data between two asynchronous clock domains
  ☆16Updated 8 years ago
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆12Updated 4 years ago
• ahmad2smile / SHA256_Verilog
  Verilog based FPGA Design of SHA256 Simulated on ModelSim
  ☆19Updated 6 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆22Updated 6 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆46Updated 8 years ago
• secworks / sha512
  Verilog implementation of the SHA-512 hash function.
  ☆37Updated 3 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆28Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆27Updated 3 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆35Updated 9 months ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• HeerAmbavi / RSAonVerilog
  Implementation of RSA algorithm on FPGA using Verilog
  ☆26Updated 6 years ago
• poucotm / SublimeLinter-contrib-verilator
  👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
  ☆14Updated 4 months ago
• raya4213 / VerilogCodeECC
  Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
  ☆22Updated 7 years ago
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆63Updated 6 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆55Updated 2 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆26Updated 3 years ago
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆22Updated 5 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 10 months ago
• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆31Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆44Updated 3 years ago
• WayneGong / Verilog_Module
  常用Verilog模块
  ☆17Updated 4 years ago