Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.
☆16Oct 16, 2018Updated 7 years ago
Alternatives and similar repositories for VerilogSHA256Miner
Users that are interested in VerilogSHA256Miner are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆26Oct 8, 2020Updated 5 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- Library of generic verilog buildingblocks☆17Dec 25, 2025Updated 9 months ago
- All Digital Phase-Locked Loop☆15May 22, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- SpringBoot 各模块整合 - 入门项目，包含：atomikos, shiro, mybatis, mybatis-plus, jpa, jdbc-template, redis, mongodb, docker, jpa, admin, asynchronous, …☆12Jul 20, 2023Updated 3 years ago
- Small example of using Metal in Swift☆11Jul 28, 2016Updated 10 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- BLE button app on Android☆10Jul 4, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An Open Source FPGA GroestlCoin Miner☆10Feb 11, 2018Updated 8 years ago
- Recording and playing uncompressed audio using AVAudioEngine☆12Jul 10, 2022Updated 4 years ago
- Prototype for an in memory fuzzer☆13Aug 1, 2017Updated 9 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Joker TV (USB) FPGA verilog/vhdl code☆16May 19, 2026Updated 4 months ago
- Uart transport + image processing + VGA display 基于FPGA的图像处理，包括Uart和VGA☆22Mar 10, 2020Updated 6 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- Official Cpp implementation of the Ambr protocol http://www.ambr.org/☆12Nov 20, 2018Updated 7 years ago
- Hardware implementation of the SHA-256 cryptographic hash function☆390Dec 15, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆28Jan 6, 2023Updated 3 years ago
- ☆20Aug 10, 2020Updated 6 years ago
- Computer Graphics Metafile☆10Apr 12, 2021Updated 5 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆17Dec 9, 2018Updated 7 years ago
- ☆17Jul 21, 2017Updated 9 years ago
- 6502 CPU in 4 small CPLDs☆28May 3, 2022Updated 4 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆17Jan 10, 2018Updated 8 years ago
- FPGA miner for OdoCrypt☆13Jul 25, 2019Updated 7 years ago
- The complete project for my tutorial on how to render a circle to the screen using Metal Shaders☆16Apr 22, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 一些经典且高质量的电子书分享☆22May 7, 2019Updated 7 years ago
- Design a new OFDM synchronization algorithm, and implement it with both Matlab and Verilog.☆21Feb 8, 2017Updated 9 years ago
- open cv software isp study☆18Nov 9, 2020Updated 5 years ago
- VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin☆64Feb 7, 2018Updated 8 years ago
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- Sample of Drawing a View’s Contents with MetalKit framework 🎨☆21Aug 19, 2019Updated 7 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago