JeremyV2014 / VerilogSHA256MinerLinks
Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.
☆16Updated 6 years ago
Alternatives and similar repositories for VerilogSHA256Miner
Users that are interested in VerilogSHA256Miner are comparing it to the libraries listed below
Sorting:
- SHA-256 IP core for ZedBoard (Zynq SoC)☆30Updated 7 years ago
- Implementation of the SHA256 Algorithm in Verilog☆37Updated 13 years ago
- Various projects of SPI loader module for xilinx fpga☆31Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆79Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- UART 16550 core☆37Updated 10 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆23Updated 8 years ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆16Updated 5 years ago
- Gaussian noise generator Verilog IP core☆31Updated 2 years ago
- Verilog SPI master and slave☆54Updated 9 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 5 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago
- RFID tag and tester in Verilog☆38Updated 12 years ago
- USB serial device (CDC-ACM)☆39Updated 4 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆72Updated last year
- Verilog implementation of the SHA-512 hash function.☆38Updated 2 months ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆21Updated 7 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- 给定ARM Cortex-M3的软核,扩展周围的AMBA总线以及基本外设,完成在上面的汇编以及C语言的执行☆18Updated 5 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆38Updated last year
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- Video Stream Scaler☆40Updated 10 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated last month
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Updated 9 years ago